NEC PD703114 User Manual page 50

(1) Interrupt status saving registers (EIPC, EIPSW)
There are two interrupt status saving registers, EIPC and EIPSW.
Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC)
are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence
of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC,
FEPSW)).
The address of the next instruction following the instruction executed when a software exception or maskable
interrupt occurs is saved to EIPC, except for some instructions (refer to 7.8 Periods in Which CPU Does Not
Acknowledge Interrupts).
The current PSW contents are saved to EIPSW.
Since there is only one set of interrupt status saving registers, the contents of these registers must be saved
by the program when multiple interrupt servicing is enabled.
Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved (fixed to 0) for future function expansion.
When the RETI instruction is executed, the values in EIPC and EIPSW are restored to the PC and PSW,
respectively.
31
EIPC
0 0 0 0 0 0
31
EIPSW
0 0 0 0 0 0
50
CHAPTER 3 CPU FUNCTION
26 25
(PC contents saved)
0 0 0 0 0 0 0 0 0 0 0 0
User's Manual U15195EJ5V0UD
8 7
0 0 0 0 0 0 (PSW contents saved)
0
After reset
0xxxxxxxH
(x: Undefined)
0
After reset
000000xxH
(x: Undefined)