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9.1.2 Function overview (timer 0)
• 16-bit timer (TM0n) for 3-phase PWM inverter control: 2 channels
• Compare registers: 6 registers × 2 channels
• 12-bit dead-time timers (DTMn0 to DTMn2): 3 timers × 2 channels
• Count clock division selectable by prescaler (set the frequency of the count clock to 40 MHz or less)
• Base clock (f
): 2 types (set f
CLK
f
and f
/2 can be selected
XX
XX
• Prescaler division ratio
The following division ratios can be selected according to the base clock (f
Division Ratio
• Interrupt request sources
(a) Compare-match interrupt request: 9 types
• Interrupt request signal INTCM0n3 generated by match of TM0n register count value and compare
register CM0n3
• Interrupt request signals INTCM010 to INTCM012, INTCM0n4, and INTCM0n5 generated by match of
TM0n register count value and compare registers CM010 to CM012, CM0n4, and CM0n5
CM010 to CM012, CM0n4, CM0n5 ≤ CM0n3
CM010 to CM012, CM0n4, CM0n5 = 0000H
CM010 to CM012, CM0n4, CM0n5 > CM0n3
(b) Underflow interrupt request: 2 types
• Interrupt request signal INTTM0n generated by underflow of the TM0n register
• External pulse output (TO0n0 to TO0n5): 6 × 2 channels
Remark
f
: Internal system clock
XX
n = 0, 1
196
CHAPTER 9 TIMER/COUNTER FUNCTION
to 40 MHz or less)
CLK
Base Clock (f
f
Selected
XX
1/1
f
XX
1/2
f
/2
XX
1/4
f
/4
XX
1/8
f
/8
XX
1/16
f
/16
XX
1/32
f
/32
XX
Setting Condition
User's Manual U15195EJ5V0UD
).
CLK
)
CLK
f
/2 Selected
XX
f
/2
XX
f
/4
XX
f
/8
XX
f
/16
XX
f
/32
XX
f
/64
XX
INTCM010 to INTCM012,
INTCM0n4, INTCM0n5 Signal
Occurrence Status
Occurs
Occurs
Does not occur
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