Halt Mode - NEC PD703114 User Manual

8.5.3 HALT mode

(1) Setting and operation status
In the HALT mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the
operation clock of the CPU is stopped. Since the supply of clocks to on-chip peripheral I/O units other than
the CPU continues, operation continues. The power consumption of the overall system can be reduced by
setting the system to HALT mode while the CPU is idle.
The system is switched to HALT mode by the HALT instruction.
Although program execution stops in the HALT mode, the contents of all registers, internal RAM, and ports
are maintained in the state they were in immediately before HALT mode began. Also, operation continues for
all on-chip peripheral I/O units (other than ports) that do not depend on CPU instruction processing. Table 8-2
shows the status of each hardware unit in the HALT mode.
Clock generator
Internal system clock
CPU
Ports
On-chip peripheral I/O (excluding ports)
Internal data
AD0 to AD15
A16 to A21
RD, ASTB
UWR, LWR
WAIT
CLKOUT
CHAPTER 8 CLOCK GENERATION FUNCTION
Table 8-2. Operation Status in HALT Mode
Function
User's Manual U15195EJ5V0UD
Operation Status
Operating
Operating
Stopped
Maintained
Operating
All internal data such as CPU registers, statuses, data,
and the contents of internal RAM are maintained in the
state they were in immediately before HALT mode
began.
Operating
Clock output
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