NEC PD703114 User Manual page 356

V850e/ia2 32-bit single-chip microcontrollers

Table of Contents

Figure 9-75. Capture Operation: 32-Bit Cascade Operation Mode (When CMSEx Register's

TByE1 Bit = 1, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = Arbitrary,

EEVEy Bit = 1, and CSCE0 Register's SEVEy Bit = 0)

READ_ENABLE_P

CVSEm0 register

CVPEm0 register

TM21 performs a count operation when, in the 32-bit mode, CASC (CNT = MAX. for TM20) is input to

TM21 and the rising edge of CTC is detected.

If an event occurs during this timing, it is ignored.

CPU read access is not performed at this timing (wait status).

Remarks 1. f

: Base clock

2. CAPTURE_P: Capture trigger signal of main capture register

CAPTURE_S: Capture trigger signal of sub capture register

CASC: TM21 count signal in 32-bit mode

CNT: Count value of timer 2

ED1: Capture event signal input from edge selector

MUXCNT: Count value to subchannel m

MUXTB0, MUXTB1: Multiplex signal of TM20, TM21

READ_ENABLE_P: Read timing of CVPEm0 register

TB0: Count value of TM20

TB1: Count value of TM21

TCOUNTE0, TCOUNTE1: Count enable signal input of timer 2

3. m = 1 to 4, x = 12, 34

y: When x = 12, y = 1, 2, and when x = 34, y = 3, 4

CHAPTER 9 TIMER/COUNTER FUNCTION

FFFEH 1234H FFFFH

User's Manual U15195EJ5V0UD

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