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ANIn0
ANIn1
ANIn2
ANIn3
ANIn4
ANIn5
ANI16
ANI17
f
/2
XX
INTADn
ITRG0
ADTRGn
Trigger source switching
circuit in timer trigger
mode (See Figure 11-2)
15
ADSCMn0 (16)
Remark
n = 0, 1
f
: Internal system clock
XX
Cautions 1. Noise at an analog input pin (ANI0m, ANI1n) or reference voltage input pin (AV
give rise to an invalid conversion result (m = 0 to 5, n = 0 to 7).
Software processing is needed in order to prevent this invalid conversion result from
adversely affecting the system.
The following are examples of software processing.
• Use the average value of the results of multiple A/D conversions as the A/D conversion
result.
• Perform A/D conversion several times consecutively and use conversion results omitting
any abnormal conversion results that are obtained.
• If an A/D conversion result from which it is judged that an abnormality occurred in the
system is obtained, be sure to recheck the abnormality occurrence before performing
malfunction processing.
2. Be sure that voltages outside the range [AV
being used as A/D converter 0 and 1 input pins.
514
CHAPTER 11 A/D CONVERTER
Figure 11-1. Block Diagram of A/D Converter 0 or 1
Sample and
hold circuit
Controller
0
15
0
15
ADSCMn1 (16)
ADETM0 (16)
16
16
Internal bus
User's Manual U15195EJ5V0UD
0
15
0
ADETM1 (16)
16
16
to AV
, AV
to AV
SS0
DD0
SS1
Comparator
AV
DDn
and D/A
AV
converter
SSn
SAR (10)
10
9
0
ADCRn0
ADCRn1
ADCRn2
INTDETn
ADCRn3
ADCRn4
ADCRn5
ADCR16
ADCR17
10
, AV
) may
DD0
DD1
] are not applied to pins
DD1
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