NEC PD703114 User Manual page 252

Figure 9-23. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx > CM0n3) (2/2)
(b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5)
count value
BFCMnx
CM0nx
Interrupt request
Remarks 1. n = 0, 1
2. x = 4, 5
3. b > CM0n3
4. INTCM0nx is generated on a match between TM0n and CM0nx (a in the above figure).
When a value greater than CM0n3 is set to BFCMn0 to BFCMn2, the positive phase side (TO0n0,
TO0n2, TO0n4 pins) outputs a high level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins)
continues to output a low level. This feature is effective for outputting a low-level or high-level width
exceeding the PWM cycle in an application such as inverter control.
The above explanation applies to an active high case. In an active low case, the levels of positive and
negative phases are merely inverted and other operations remain the same.
Figure 9-24 shows the change timing from the 100% duty state.
252
CHAPTER 9 TIMER/COUNTER FUNCTION
CM0n3
a
TM0n
0000H
CM0nx
match
a b
a
INTCM0n3
INTCM0nx
User's Manual U15195EJ5V0UD
CM0n3
b b
b b
INTTM0n INTCM0n3
b
b b
INTTM0n