HP E1313A Manual page 382

High speed a/d module
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Control Processor
States
Reset and Abort are bits written to the
VXI Control Register (Base + 04
Passed and Ready are bits read from the
VXI Status Register (Base + 04
Running* is a bit read from the Scan Status
Register (Base + 10
).
16
ARM is a Register-Based command sent to the
Command and Parameter Registers (Base + 08
through 0E
).
16
Running*
Asserted
Appendix D
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Figure D-7 shows the relationships between the control processor's states.
Reset
).
16
).
16
16
Abort
set
Abort
Abort
clear
Abort
Abort
complete
set
set
Scanning
trigger
event
Figure D-7. Control Processor State Diagram
Self-Test
Passed
and Ready
Ready for
Command
scan
ARM
command
Armed
Register-Based Programming
Running*
Asserted
381

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