Vxi Control Register Base + 04 - HP E1313A Manual

Status Bit Precedence
VXI Control Register
340 Register-Based Programming
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The validity of this bit is determined by bit 0, and in turn, bit 7 determines
the validity of bit 1. See " Status Bit Precedence" for more information.
NOERR: A zero (0) in bit 6 indicates that an error has occurred.
Ready: A zero (0) in bit 3 with a one (1) in bit 2 indicates that the module
has not completed its initialization process.
Passed: A zero (0) in bit 2 indicates that the module is executing a reset or
has failed it self-test. A one (1) in bit 2 indicates that the reset has finished
or the self-test passed.
Query/Resp Ready: A one (1) in bit 1 indicates that data returned by a
query command is available in the Query Response Register. The bit is
cleared (0) when the register is read.
Cmd/Parm Ready: A one (1) in bit 0 indicates that a command or
parameter op code can be written to the Command or Parameter Register.
The bit is cleared (0) when the Command Register is written to.
Certain Status bits indicate the validity of other bits in the Status Register.
This solves race condition between the selected bits.
When Cmd/Parm Ready is zero (0), DONE is invalid. This allows the
module to clear DONE to indicate that a command is being processed.
When DONE is zero (0), NOERR and Query/Resp Ready are invalid. This
allows the module to set those bits to the correct states based on the
conditions they represent.
Write only: The Control Register is used to reset the module, and to disable
the module from driving the SYSFAIL line.
Address 15
Base + 04 A24 Enable
16
A24 Enable: Writing a one (1) to bit 15 enables accesses to the A24 address
space. Writing a zero (0) disables accesses to the A24 address space.
SYSINH: Writing a one (1) to bit 1 prevents the module from asserting the
SYSFAIL line. Writing a zero (0) allows the module to assert SYSFAIL.
RESET: Writing a one (1) to bit 0 resets the module. Writing a zero (0) turns
the reset function off. While bit 0 is 1, the module is held in the reset state.
14 - 2 1 0
unused SYSINH RESET
Base + 04
16
Appendix D