HP E1313A Manual page 349

Address 15
Base + 16 Limit Test
16
Exceeded
348 Register-Based Programming
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Level Interrupts:
FIFO Half Full
–
Strobed Interrupts:
FIFO Overflowed
–
Meas Complete
–
Over voltage Detect
–
Trigger Too Fast
–
SCP Trigger
–
Limit Test Exceeded
–
14 13 12
SCP Trig Meas Trig Too
Complete Fast
A one (1) in a bit indicates that the interrupt source is asserted. A zero (0)
in a bit indicates that the interrupt source is de-asserted.
Limit Test Exceeded: This bit will be set to one (1) at the end of each Scan
List in which a channel has exceeded its limit test.
SCP Trigger: A one (1) in this bit indicates that a Signal Conditioning Plug-on
(SCP) has triggered. A zero (0) indicates that an SCP has not triggered.
Measurement Complete: A one (1) indicates that the measurement has
completed.
Trigger Too Fast: A one (1) in this bit indicates that a trigger too fast
condition has been detected. A zero (0) indicates that no trigger too fast
condition has occurred.
Over Voltage Detect: A one (1) indicates that an SCP over voltage condition
has occurred. A zero (0) indicates that no over voltage condition has occurred.
Scan Complete: A one indicates that the module has completed a scan. If
the module is in the Free-run mode, Scan Complete is asserted at the end of
each scan.
FIFO Overflowed: A one (1) indicates that the FIFO has overflowed.
FIFO Half Full: A one (1) indicates that the FIFO is half. To clear this
condition, the FIFO is read until the FIFO is less than half full.
11 10 9
Over V Scan FIFO
Detect Complete Over-
flowed
8
7 - 0
FIFO not used
Half Full
Appendix D