Table 2-1 Table Of Reset And Interrupt Vectors - Fujitsu MB89140 Series Hardware Manual

CPU
HARDWARE CONFIGURATION
I/O area
This area is where various resources such as control and data registers are
located. The memory map for the I/O area is given in APPENDIX A.
RAM area
This area is where the static RAM is located. Addresses from 0100
are also used as the general-purpose register area.
01FF
H
ROM area
This area is where the internal ROM is located. Addresses from FFC0
are also used for the table of reset and vector-call instructions.
FFFF
H
Table 2-1 shows the correspondence between each interrupt number or re-
set and the table addresses to be referenced for the MB89145 series of mi-
crocontrollers.

Table 2-1 Table of Reset and Interrupt Vectors

Table address
Upper data Lower data
CALLV #0 FFC0
H
CALLV #1 FFC2
H
CALLV #2 FFC4
H
CALLV #3 FFC6
H
CALLV #4 FFC8
H
CALLV #5 FFCA
H
CALLV #6 FFCC
H
CALLV #7 FFCE
H
2-4
Upper data
FFC1 Interrupt #11
H
FFC3 Interrupt #10
H
FFC5 Interrupt #9
H
FFC7 Interrupt #8
H
FFC9 Interrupt #7
H
FFCB Interrupt #6
H
FFCD Interrupt #5
H
FFCF Interrupt #4
H
Interrupt #3
Interrupt #2
Interrupt #1
Interrupt #0
Reset mode
Reset vector
Note: FFFC is already reserved.
H
to
H
to
H
Table address
Lower data
FFE4 FFE5
H H
FFE6 FFE7
H H
FFE8 FFE9
H H
FFEA FFEB
H H
FFEC FFED
H H
FFEE FFEF
H H
FFF0 FFF1
H H
FFF2 FFF3
H H
FFF4 FFF5
H H
FFF6 FFF7
H H
FFF8 FFF9
H H
FFFA FFFB
H H
––––– FFFD
H
FFFE FFFF
H H