Asynchronous Signals Design Guidelines; Asynchronous Signals General Introduction; Description; Asynchronous Signal Descriptions - Intel Quark SoC X1000 Design Manual

Asynchronous Signals Design Guidelines—Intel
13.0

Asynchronous Signals Design Guidelines

13.1

Asynchronous Signals General Introduction

13.1.1

Description

This section describes the topologies and layout recommendations for the
asynchronous signals. Refer to the Intel
13.2

Asynchronous Signal Descriptions

13.2.1

Signal Groups

Table 48.

Asynchronous Legacy Signal Group

Signal Name
GPIO[7:0]
13.3

Asynchronous Signals Topology Guidelines

This section describes topologies and layout recommendations for the legacy signals.
Although these signals toggle with relatively low frequency, most of them have very
high-edge rates.
Warning: Inappropriate routing or lack of termination can seriously decrease signal quality and
lead to electrical specification violations and even logical system failures. The following
guidelines apply to all legacy signals described in this section.
• Watch for termination recommendations. If any of the signals that require platform
termination are pulled-up to a voltage higher than VCCST then the reliability and
power consumption of the SOC may be affected. Therefore, it is very important to
follow the recommended pull-up voltage for these signals.
• The routing guidelines allow the asynchronous signals to be routed using microstrip
using 50 ±15% characteristic trace impedance
• Changing reference plane is not recommended and may cause signal integrity
degradation. In any case, if such routing can't be avoided, use stitching vias and
bypass capacitors between the reference planes near the layer transition.
General trace spacing requirements (for 50  characteristic impedance traces) specified
in the following table. W is trace width and S is the space between 2 adjacent traces.
Table 49.

Asynchronous Signal General Routing Guideline

Trace Type
Microstrip
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
®
Quark SoC X1000 Datasheet for more details.
General Purpose IO configurable in direction.
Stackup
Units
(MS/SL/DSL)
MS mils
Description
Trace Width (W) Minimum Spacing (S)
4
®
Intel
12
Quark™ SoC X1000
PDG
93