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NEC mPD780812 Preliminary User's Manual

8-bit single-chip microcontroller

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Preliminary User's Manual

µPD780812

µPD780814

µPD78F0818

8-bit Single-Chip Microcontroller

Hardware

Document No. U13413EE1V0UM00

Date Published April 1998

© NEC Corporation 1998

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Page 1 Preliminary User’s Manual µPD780812 µPD780814 µPD78F0818 8-bit Single-Chip Microcontroller Hardware Document No. U13413EE1V0UM00 Date Published April 1998 © NEC Corporation 1998...
Page 2 Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance.
Page 3: Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 4 µPD780812, µPD780814, µPD78F0818 Introduction Readers This manual has been prepared for user engineers who want to understand the functions of the µPD780814 subseries and design and develop its application systems and programs. µPD780814 Subseries: µPD780812, µPD780814, µPD78F0818 Purpose This manual is intended for users to understand the functions described in the Organization below. Organization The µPD780814 subseries manual is separated into two parts: this manual and the instruction edition (common to the 78K/0 series).
Page 5 µPD780812, µPD780814, µPD78F0818 Chapter Organization This manual devides the descriptions for the subseries into different chapters as shown below. Read only the chapters related to the device you use. Chapter µPD780812 µPD780814 µPD78F0818 ‰ ‰ ‰ Chapter 1 Outline (µPD780814 Subseries) ‰...
Page 6 µPD780812, µPD780814, µPD78F0818 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Related documents for µPD780814 subseries D ocum ent N o. D ocum ent nam e Japanese English µPD 780814 Prelim inary Product Inform ation...
Page 7 C10943X IEI-1213 Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E Reliability Quality Control on NEC Semiconductor Devices C10983J C10983E Electric Static Discharge (ESD) Test MEM-539 — Semiconductor Devices Quality Assurance Guide MEI-603 MEI-1202...
Page 8: Table Of Contents
µPD780812, µPD780814, µPD78F0818 Contents Chapter 1 Outline (µPD780814 Subseries) ..................Features ..........................Application ........................... Ordering Information ......................Pin Configuration (Top View) ....................78K/0 Series Development ....................Block Diagram ........................Overview of Functions ......................Differences between Flash and Mask ROM version ............Chapter 2 Pin Function (µPD780814 Subseries) ................
Page 9 µPD780812, µPD780814, µPD78F0818 Processor Registers ......................3.2.1 Control registers ...................... 3.2.2 General registers ...................... 3.2.3 Special function register (SFR) ................Instruction Address Addressing ..................3.3.1 Relative addressing ....................3.3.2 Immediate addressing ..................... 3.3.3 Table indirect addressing ..................3.3.4 Register addressing ....................Operand Address Adressing ....................
Page 10 µPD780812, µPD780814, µPD78F0818 Chapter 6 Clock Generator ......................Clock Generator Functions ....................Clock Generator Configuration .................... Clock Generator Control Register ..................System Clock Oscillator ...................... 100 6.4.1 Main system clock oscillator .................. 100 6.4.2 Subsystem clock oscillator ..................101 6.4.3 When no subsystem clocks are used ..............
Page 11 µPD780812, µPD780814, µPD78F0818 Chapter 10 8-Bit Timer/Event Counters 50 and 51 ................ 158 10.1 8-Bit Timer/Event Counters 50 and 51 Functions .............. 158 10.1.1 8-Bit Operation Modes ..................... 159 10.1.2 16-Bit Operation Modes ................... 161 10.2 8-Bit Timer/Event Counters 50 and 51 Configurations ............. 162 10.3 8-Bit Timer/Event Counters 50 and 51 Control Registers ..........
Page 12 µPD780812, µPD780814, µPD78F0818 Chapter 14 A/D Converter ........................ 204 14.1 A/D Converter Functions ..................... 204 14.2 A/D Converter Configuration ....................205 14.3 A/D Converter Control Registers ..................207 14.4 A/D Converter Operations ....................210 14.4.1 Basic operations of A/D converter ................210 14.4.2 Input voltage and conversion result ...............
Page 13 µPD780812, µPD780814, µPD78F0818 Chapter 18 CAN Controller ......................259 18.1 Protocol ..........................260 18.1.1 Protocol mode function ................... 260 18.1.2 Message format ......................260 18.1.3 Data frame/remote frame ..................261 18.1.4 Error frame ....................... 266 18.1.5 Overload frame ......................267 18.2 Function ..........................
Page 14 µPD780812, µPD780814, µPD78F0818 18.18 Functional Description by Flowcharts ................322 18.18.1 Initialization ......................322 18.18.2 Prepare transmit ....................323 18.18.3 Abort transmit ....................... 324 18.18.4 Handling by the DCAN ..................325 18.18.5 Receive event oriented ..................326 18.18.6 Receive task oriented ................... 327 Chapter 19 Interrupt Functions .......................
Page 15 µPD780812, µPD780814, µPD78F0818 Chapter 23 µPD78F0818 ........................368 23.1 Memory Size Switching Register (IMS) ................369 23.2 Internal Extension RAM Size Switching Register .............. 370 23.3 Flash Memory Programming ....................371 23.3.1 Selection of transmission method ................371 23.3.2 Initialization of the programming mode ..............371 23.3.3 Flash memory programming function ..............
Page 16 µPD780812, µPD780814, µPD78F0818 Contents of Figures Figure No. Title Page Pin Configuration ......................Block Diagram ........................ Connection of IC Pins ..................... Pin Input/Output Circuits (2/2) ..................Memory Map (µPD780812) ..................... Memory Map (µPD780814) ..................... Memory Map (µPD78F0818) ................... Data Memory Addressing (µPD780812) ................Data Memory Addressing (µPD780814) ................
Page 17 µPD780812, µPD780814, µPD78F0818 Figure No. Title Page Block Diagram of Clock Generator .................. Processor Clock Control Register Format ............... External Circuit of Main System Clock Oscillator ............100 External Circuit of Subystem Clock Oscillator ..............101 Examples of Oscillator with Bad Connection (3/3) ............102 Main System Clock Stop Function (1/2) ................
Page 18 µPD780812, µPD780814, µPD78F0818 Figure No. Title Page Timer 0 (TM0) Block Diagram ..................148 16-Bit Timer Mode Control Register (TMC2) Format ............150 Capture Pulse Control Register (CRC2) Format ............... 151 Prescaler Mode Register (PRM2) Format ................ 152 Configuration Diagram for Pulse Width Measurement by Using the Free Running Counter....................
Page 19 µPD780812, µPD780814, µPD78F0818 Figure No. Title Page 13-1 Remote Controlled Output Application Example .............. 199 13-2 Clock Output Control Circuit Block Diagram ..............200 13-3 Clock Output Selection Register (CKS) Format ............... 201 13-4 Port Mode Register 2 Format ..................202 14-1 A/D Converter Block Diagram ..................
Page 20 µPD780812, µPD780814, µPD78F0818 Figure No. Title Page 18-1 Data Frame ........................261 18-2 Remote Frame ........................ 261 18-3 Data Frame ........................262 18-4 Arbitration Field/Standard Format Mode ................262 18-5 Arbitration Field/Expanded Format Mode ................ 262 18-6 Control Field ........................263 18-7 Data Field ........................
Page 21 µPD780812, µPD780814, µPD78F0818 Figure No. Title Page 18-46 Receive Message Register ..................... 315 18-47 Mask Control Register ....................316 18-48 Redefinition Control Register ................... 318 18-49 Initialization Flow Chart ....................322 18-50 Transmit Preparation ....................... 323 18-51 Transmit Abort, Software Flow ..................324 18-52 Handling of Semaphore Bits by DCAN-Module ..............
Page 22 µPD780812, µPD780814, µPD78F0818 Figure No. Title Page 22-1 Block Diagram of RESET Function ................. 362 22-2 Timing of Reset Input by RESET Input ................363 22-3 Timing of Reset due to Watchdog Timer Overflow ............363 22-4 Timing of Reset Input in STOP by RESET Input ............. 363 23-1 Memory Size Switching Register Format ................
Page 23 µPD780812, µPD780814, µPD78F0818 Contents of Tables Table No. Title Page Differences between Flash and Mask ROM version ............Pin Input/Output Types ....................... Non-Port Pins ........................Types of Pin Input/Output Circuits ..................Internal ROM Capacities ....................Vectored Interrupts ......................Special Function Register List (3/3) ................... Implied Addressing ......................
Page 24 µPD780812, µPD780814, µPD78F0818 Table No. Title Page 10-11 8-Bit Timer/Event Counters 51 Square-Wave Output Ranges (8-Bit Timer/Event Counter Mode) ..................176 10-12 8-Bit Timer/Event Counters Interval Times (16-Bit Timer/Event Counter Mode) ....182 10-13 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges (16-Bit Timer/Event Counter Mode) ..................
Page 25 µPD780812, µPD780814, µPD78F0818 Table No. Title Page 18-15 Error Counter ........................271 18-16 Segment Name and Segment Length ................. 272 18-17 CAN Configuration ......................279 18-18 SFR Definitions ........................280 18-19 SFR Bit Definitions ......................280 18-20 Message and Buffer Structure ................... 281 18-21 Transmit Message Structure ....................
Page 26: Chapter 1 Outline (Μpd780814 Subseries)
µPD780812, µPD780814, µPD78F0818 Chapter 1 Outline (µPD780814 Subseries) 1.1 Features • Internal high capacity ROM and RAM Item Data Memory Program Internal Internal Memory Package Part High-Speed Expansion EEPROM (ROM) Number µPD780812 16K bytes 512 bytes 288 bytes 256 bytes 64-pin plastic QFP (fine pitch) µPD780814 32K bytes...
Page 27: Pin Configuration (Top View)
µPD780812, µPD780814, µPD78F0818 1.4 Pin Configuration (Top View) Ý 64-pin plastic QFP (12 x 12 mm) µPD780812GK-XXX-8A8 µPD780814GK-XXX-8A8 µPD78F0818GK-XXX-8A8 Figure 1-1: Pin Configuration Cautions: 1. Connect IC (internally connected) pin directly to V 2. AV pin should be connected to V 3.
Page 28 µPD780812, µPD780814, µPD78F0818 Pin Identifications P00 to P03 : Port0 : Receive Data P10 to P17 : Port1 : Transmit Data P20 to P27 : Port2 : Programmable Clock Output P40 to P47 : Port4 X1, X2 : Crystal (Main System Clock) P50 to P57 : Port5 CL1, CL2...
Page 29: Series Development
µPD780812, µPD780814, µPD78F0818 1.5 78K/0 Series Development These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I C bus.
Page 30: Block Diagram
µPD780812, µPD780814, µPD78F0818 1.6 Block Diagram Figure 1-2: Block Diagram TI00/TO0 16 bit Timer 0 TI01 Port 0 TI20 16 bit Timer 2 TI21 16 K / 32 K TI22 78K/0 512 Bytes / Port 1 1024 Bytes / TI50/TO50 8 bit Timer 50 Core 1024 Bytes...
Page 31: Overview Of Functions
µPD780812, µPD780814, µPD78F0818 1.7 Overview of Functions Part Number D780812 D780814 D78F0818 Item 16 K bytes 32 K bytes 60 K bytes Internal high-speed 512 Bytes 1024 Bytes 1024 Bytes Internal memory Internal expansion RAM 288 Bytes 288 Bytes 992 Bytes EEPROM 256 K bytes Memory space...
Page 32: Differences Between Flash And Mask Rom Version
µPD780812, µPD780814, µPD78F0818 1.8 Differences between Flash and Mask ROM version The differences between the two versions are shown in the table below. Differences of the electrical specification are given in the data sheet. Table 1-1: Differences between Flash and Mask ROM version Flash Version Mask ROM Version Flash EEPROM...
Page 33 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 34: Chapter 2 Pin Function (Μpd780814 Subseries)
µPD780812, µPD780814, µPD78F0818 Chapter 2 Pin Function (µPD780814 Subseries) 2.1 Pin Function List Normal Operating Mode Pins / Pin Input/Output Types Table 2-1: Pin Input/Output Types Input / After Pin Name Function Alternate Function Output Reset INTP0 Input Port 0 4 bit input / output port INTP1 Input...
Page 35: Non-Port Pins
µPD780812, µPD780814, µPD78F0818 2.2 Non-Port Pins Table 2-2: Non-Port Pins Alternate After Pin Name Function Function Reset INTP0 External interrupts with specifiable valid INTP1 Input edges (rising edge, falling edge, both rising Input INTP2 and falling edges) INTP3 Input Serial interface serial data input Input Output Serial interface serial data output...
Page 36: Description Of Pin Functions
µPD780812, µPD780814, µPD78F0818 2.3 Description of Pin Functions 2.3.1 P00 to P03 (Port 0) This is an 4-bit input/output port. Besides serving as input/output port the external interrupt input is implemented. (1) Port mode P00 to P03 function as input/output ports. P00 to P03 can be specified for input or output bitwise with a port mode register.
Page 37: P40 To P47 (Port 4)
µPD780812, µPD780814, µPD78F0818 (c) TI50 Pin for external count clock input to 8-bit timer/event counter 50. (d) TO50 Pin for output of the 8-bit timer/event counter 50. (e) TI51 Pin for external count clock input to 8-bit timer/event counter 51. (f) TO51 Pin for output of the 8-bit timer/event counter 51.
Page 38: P70, P71 (Port 7)
µPD780812, µPD780814, µPD78F0818 (2) Control mode These ports function as timer capture input. (a) TI20, TI21, TI22 Pins for external capture trigger input to the 16-bit timer capture registers of TM2. 2.3.7 P70, P71 (Port 7) These are 2-bit input/output ports. Besides serving as input/output ports, they function timer input/output. The following operating modes can be specified bit-wise or byte-wise.
Page 39: Reset
µPD780812, µPD780814, µPD78F0818 2.3.14 RESET This is a low-level active system reset input pin. 2.3.15 X1 and X2 Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to 2.3.16 CL1 and CL2 RC connect pins for sub system clock oscillation. 2.3.17 VDD0, VDD1 VDD0 is the positive power supply pin for ports.
Page 40: Pin I/O Circuits And Recommended Connection Of Unused Pins
µPD780812, µPD780814, µPD78F0818 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in the following table. For the input/output circuit configuration of each type, see table. Table 2-3: Types of Pin Input/Output Circuits (1/2) Input/Output Recommended Connection...
Page 41: Pin Input/Output Circuits (2/2)
µPD780812, µPD780814, µPD78F0818 Table 2-3: Types of Pin Input/Output Circuits (2/2) Input/Output Recommended Connection Pin Name Circuit Type for Unused Pins Connect to Vdd or Vss via CRxD a resistor individually CTxD CL1/CCLK or GND Leave open RESET Connect to V Connect to V Connect directly to V...
Page 42 µPD780812, µPD780814, µPD78F0818 Figure 2-2: Pin Input/Output Circuits Type 1 Type 2 P-ch Data N-ch Type 5-A Type 8-A Pullup Pullup P-ch P-ch enable enable Data Data P-ch P-ch IN/OUT IN/OUT Output Output N-ch N-ch disable disable Input enable Type 11-B Type 10-A Pullup P-ch...
Page 43 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 44: Chapter 3 Cpu Architecture
µPD780812, µPD780814, µPD78F0818 Chapter 3 CPU Architecture 3.1 Memory Space The memory map of the µPD780812 is shown in Figure 3-1. Figure 3-1: Memory Map (µPD780812) FFFFH Special Function Register (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH...
Page 45: Memory Map (Μpd780814)
µPD780812, µPD780814, µPD78F0818 The memory map of the µPD780814 is shown in Figure 3-2. Figure 3-2: Memory Map (µPD780814) FFFFH Special Function Registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH Internal High-speed RAM 1024 x 8 bits FE20H...
Page 46: Memory Map (Μpd78F0818)
µPD780812, µPD780814, µPD78F0818 The memory map of the µPD78F0818 is shown in Figure 3-3. Figure 3-3: Memory Map (µPD78F0818) FFFFH Special Function Registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH Internal High-speed RAM 1024 x 8 bits FE20H...
Page 47: Internal Program Memory Space
µPD780812, µPD780814, µPD78F0818 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This is generally accessed by the program counter (PC). The µPD780814 subseries have various size of internal ROMs or Flash EPROM as shown below. Table 3-1: Internal ROM Capacities Part Number Internal ROM...
Page 48: Vectored Interrupts
µPD780812, µPD780814, µPD78F0818 (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.
Page 49: Internal Data Memory Space
µPD780812, µPD780814, µPD78F0818 3.1.2 Internal data memory space The µPD780814 subseries units incorporate the following RAMs. (1) Internal high-speed RAM The 32-byte area FEE0H to FEFF is allocated with four general purpose register banks composed of 8-bit banks. The internal high-speed RAM can also be used as a stack memory. Product Internal High Speed RAM µPD780812...
Page 50: Data Memory Addressing
µPD780812, µPD780814, µPD78F0818 3.1.4 Data memory addressing The µPD780814 subseries is provided with a varity of addressing modes which take account of memory manipulability, etc. Special addressing methods are possible to meet the functions of the special function registers (SFRs) and general registers. The data memory space is the entire 64K-byte space (0000H to FFFFH).
Page 51: Data Memory Addressing (Μpd780814)
µPD780812, µPD780814, µPD78F0818 Figure 3-5: Data Memory Addressing (µPD780814) FFFFH Special Function Register (SFR) 256 x 8 bits SFR Addressing FF20H FF1FH FF00H Short Direct FEFFH General Registers Register Addressing Addressing 32 x 8 bits FEE0H FEDFH Internal High-speed RAM 1024 x 8 bits FE20H FB00H...
Page 52: Data Memory Addressing (Μpd78F0818)
µPD780812, µPD780814, µPD78F0818 Figure 3-6: Data Memory Addressing (µPD78F0818) FFFFH Special Function Register (SFR) 256 x 8 bits SFR Addressing FF20H FF1FH FF00H FEFFH Short Direct General Registers Register Addressing Addressing 32 x 8 bits FEE0H FEDFH Internal High-speed RAM 1024 x 8 bits FE20H FB00H...
Page 53: Processor Registers
µPD780812, µPD780814, µPD78F0818 3.2 Processor Registers The µPD780814 subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses, and stack memory. The control registers consist of a program counter, a program status word and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 54 µPD780812, µPD780814, µPD78F0818 (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to interrupt disabled (DI) status. All interrupts except non-maskable interrupt are disabled. When 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledge is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag.
Page 55: Stack Pointer Configuration
µPD780812, µPD780814, µPD78F0818 (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high- speed RAM area can be set as the stack area. Figure 3-9: Stack Pointer Configuration The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory.
Page 56: General Registers
µPD780812, µPD780814, µPD78F0818 3.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can also be used as an 8-bit register.
Page 57: Special Function Register (Sfr)
µPD780812, µPD780814, µPD78F0818 3.2.3 Special function register (SFR) Unlike a general register, each special function register has special functions. It is allocated in the FF00H to FFFFH area. The special function registers can be manipulated in a similar way as the general registers, by using operation, transfer, or bit-manipulate instructions.
Page 58: Special Function Register List (3/3)
µPD780812, µPD780814, µPD78F0818 Table 3-3: Special Function Register List (1/3) Manipulatable Bit Unit After Address SFR Name Symbol Reset 1 bit 8 bits 16 bits ‰ ‰ FF00H Port 0 — ‰ ‰ FF01H Port 1 — ‰ ‰ FF02H Port 2 —...
Page 59 µPD780812, µPD780814, µPD78F0818 Table 3-3: Special Function Register List (2/3) Manipulatable Bit Unit After Address SFR Name Symbol Reset 1 bit 8 bits 16 bits FF68H TM2L ‰ 16-bit timer/counter register 2 — — FF69H TM2H FF6AH CR20L ‰ 16-bit capture register 20 CR20 —...
Page 60 µPD780812, µPD780814, µPD78F0818 Table 3-3: Special Function Register List (3/3) Manipulatable Bit Unit After Address SFR Name Symbol Reset 1 bit 8 bits 16 bits ‰ ‰ FFE0H Interrupt request flag register 0L IF0L ‰ ‰ ‰ FFE1H Interrupt request flag register 0H IF0H ‰...
Page 61: Instruction Address Addressing
µPD780812, µPD780814, µPD78F0818 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 62: Immediate Addressing
µPD780812, µPD780814, µPD78F0818 3.3.2 Immediate addressing Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can branch to all the memory space. CALLF !addr11 instruction branches to the area from 0800H to 0FFFH.
Page 63 µPD780812, µPD780814, µPD78F0818 3.3.3 Table indirect addressing Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed.
Page 64: Register Addressing
µPD780812, µPD780814, µPD78F0818 3.3.4 Register addressing Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. Figure 3-16: Register Addressing...
Page 65: Operand Address Adressing
µPD780812, µPD780814, µPD78F0818 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed.
Page 66: Register Addressing
µPD780812, µPD780814, µPD78F0818 3.4.2 Register addressing The general register is accessed as an operand. The general register to be accessed is specified with register bank select flags (RBS0 and RBS1) and register specify code (Rn, RPn) in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 67: Direct Addressing
µPD780812, µPD780814, µPD78F0818 3.4.3 Direct addressing The memory indicated by immediate data in an instruction word is directly addressed. Operand format Table 3-6: Direct Addressing Identifier Description addr16 Label or 16-bit immediate data Description example MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code...
Page 68: Short Direct Addressing
µPD780812, µPD780814, µPD78F0818 3.4.4 Short direct addressing The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this addressing is applied to is the 256-byte space, from FE20H to FF1FH. An internal high-speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 69: Special Function Register (Sfr) Addressing
µPD780812, µPD780814, µPD78F0818 3.4.5 Special function register (SFR) addressing The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 70: Register Indirect Addressing
µPD780812, µPD780814, µPD78F0818 3.4.6 Register indirect addressing The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register pair specify code in the instruction code.
Page 71: Based Addressing
µPD780812, µPD780814, µPD78F0818 3.4.7 Based addressing 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified with the register bank select flags (RBS0 and RBS1).
Page 72: Based Indexed Addressing
µPD780812, µPD780814, µPD78F0818 3.4.8 Based indexed addressing The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified with the register bank select flag (RBS0 and RBS1).
Page 73 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 74: Chapter 4 Eeprom
Caution: The values shown above are target values. These values are subject to change without notice, so please contact your NEC sales representative for the latest value before designing. (4) When write is completed, interrupt request signal (INTWE) is issued.
Page 75: Eeprom Configuration
µPD780812, µPD780814, µPD78F0818 4.2 EEPROM Configuration EEPROM is composed of EEPROM itself and a control area. The control area consists of the EEPROM write control register (EEWC) that controls EEPROM writing, and an area that generates an interrupt request signal (INTWE) upon detecting write termination. Figure 4-1: EEPROM Block Diagram Internal bus EEPROM write control register (EEWC)
Page 76: Eeprom Control Register
µPD780812, µPD780814, µPD78F0818 4.3 EEPROM Control Register EEPROM is controlled with the EEPROM write control register (EEWC). EEWC is set with either a 1-bit or 8-bit memory manipulation instruction. RESET input sets EEWC to 00H. Figure 4-2: EEPROM Write Control Register (EEWC) Format After Symbol Address...
Page 77: Eeprom Reading
µPD780812, µPD780814, µPD78F0818 4.4 EEPROM Reading Reading of EEPROM data is performed with the following procedure. <1> Check that EWST (EEPROM write control register (EEWC) bit 1) is 0 (EEPROM writing is not in progress). <2> Execute read instruction. Cautions: 1.
Page 78: Eeprom Writing
µPD780812, µPD780814, µPD78F0818 4.5 EEPROM Writing Data writing to EEPROM is performed with the following procedure. <1> Check that EWST (EEPROM write control register (EEWC) bit 1) is 0 (EEPROM writing is not in progress). <2> Set the write time with EWCS0 and EWCS1 (EEWC bits 4 and 5). <3>...
Page 79 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 80: Chapter 5 Port Functions
µPD780812, µPD780814, µPD78F0818 Chapter 5 Port Functions 5.1 Port Functions The µPD780818 subseries units incorporate eight input ports and thirty-eight input/output ports. Figure 5-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on- chip hardware input/output pins.
Page 81: Pin Input/Output Types
µPD780812, µPD780814, µPD78F0818 Table 5-1: Pin Input/Output Types Input / Alternate After Pin Name Function Output Function Reset Port 0 INTP0 Input 8 bit input/output port INTP1 Input Input/ Input/output mode can be specified bit-wise Output INTP2 Input If used an input port, a pull-up resistor can be INTP3 Input connected by software bit-wise...
Page 82: Port Configuration
µPD780812, µPD780814, µPD78F0818 5.2 Port Configuration A port consists of the following hardware: Table 5-2: Port Configuration Item Configuration Port mode register (PMm: m = 0, 2, 4 to 7) Pull-up resistor option register (PUm: m = 0, 2, 4 to 7) Control register Port function register (PFm: m = 2) Note...
Page 83: Port 0
µPD780812, µPD780814, µPD78F0818 5.2.1 Port 0 Port 0 is an 4-bit input/output port with output latch. P00 to P03 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (PM0). When P00 to P03 pins are used as input ports, a pull-up resistor can be connected to them bitwise with a pull-up resistor option register (PU0).
Page 84: Port 1
µPD780812, µPD780814, µPD78F0818 5.2.2 Port 1 Port 1 is an 8-bit input only port. Dual-functions include an A/D converter analog input. Figure 5-3 shows a block diagram of port 1. Figure 5-3 P10 to P17 Configurations P10/ANI0 P14/ANI7 : Port 1 read signal...
Page 85: Port 2
µPD780812, µPD780814, µPD78F0818 5.2.3 Port 2 Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2(PM2). Dual-functions include serial interface data input/output, clock input/output. When P20 to P27 pins are used as output ports, the output buffer is selectable between CMOS-type or N-channel open drain.
Page 86: Port 4
µPD780812, µPD780814, µPD78F0818 5.2.4 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, an on-chip pull-up resistor can be connected to them bitweise with the pull-up resistor option register (PU4).
Page 87: Port 5
µPD780812, µPD780814, µPD78F0818 5.2.5 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). RESET input sets port 5 to input mode. Figure 5-7 shows a block diagram of port 5.
Page 88: Port 6
µPD780812, µPD780814, µPD78F0818 5.2.6 Port 6 Port 6 is an 8-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with a port mode register 6 (PM6). When pins P60 to P67 are used as input port pins, an on- chip pull-up resistor can be connected bitwise with a pul-up resistor option register (PU6).
Page 89: Port 7
µPD780812, µPD780814, µPD78F0818 5.2.7 Port 7 This is a 2-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with a port mode register 7. When pins P70 and P71 are used as input port pins, an on-chip pull- up resistor can be connected bitwise with a pull-up resistor option register (PU7).
Page 90: Port Function Control Registers
µPD780812, µPD780814, µPD78F0818 5.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0, PM2, PM4 to PM7) • Pull-up resistor option register (PUm : m = 0, 2, 4 to 7) •...
Page 91: Port Mode Register Format
µPD780812, µPD780814, µPD78F0818 Figure 5-10: Port Mode Register Format Symbol Address After Reset R/W PM03 PM02 PM01 PM00 FF20H PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 FF24H PM57 PM56 PM55 PM54 PM53 PM52...
Page 92: Pull-Up Resistor Option Register (Pu0, Pu2, Pu4 To Pu7) Format
µPD780812, µPD780814, µPD78F0818 (2) Pull-up resistor option registers (PU0, PU2, PU4 to PU7) These registers are used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull- up resistor use has been specified with PU0, PU2, PU4 to PU7.
Page 93: Port Function Register (Pf2) Format
µPD780812, µPD780814, µPD78F0818 3) Port function register (PF2) This register is used to set the output buffer of port 2 (P20 to P22). PF2 is set with an 1-bit or 8-bit manipulation instruction. RESET input sets this register to 00H. Figure 5-12: Port Function Register (PF2) Format After Symbol...
Page 94: Key Return Mode Register (Krm)
µPD780812, µPD780814, µPD78F0818 4) Key Return Mode (KRM) This register is used to enable/disable the key return signaling. KRM is set with an 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-13: Key Return Mode Register (KRM) After Symbol Address...
Page 95: Port Function Operations
µPD780812, µPD780814, µPD78F0818 5.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 96 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 97: Chapter 6 Clock Generator
µPD780812, µPD780814, µPD78F0818 Chapter 6 Clock Generator 6.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 4 to 8.5 MHz.
Page 98: Clock Generator Configuration
µPD780812, µPD780814, µPD78F0818 6.2 Clock Generator Configuration The clock generator consists of the following hardware. Table 6-1: Clock Generator Configuration Item Configuration Control register Processor clock control register (PCC) Oscillator Main system clock oscillator Subsystem clock oscillator Figure 6-1: Block Diagram of Clock Generator Prescaler Clock to Main...
Page 99: Clock Generator Control Register
µPD780812, µPD780814, µPD78F0818 6.3 Clock Generator Control Register The clock generator is controlled by the processor clock control register (PCC). (1) Processor clock control register (PCC) The PCC selects a CPU clock and the division ratio, determines whether to make the main system clock oscillator operate or stop.
Page 100: System Clock Oscillator
µPD780812, µPD780814, µPD78F0818 6.4 System Clock Oscillator 6.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 8.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, the clock signal to the X1 pin and an inversed phase clock signal to the X2 pin.
Page 101: Subsystem Clock Oscillator
µPD780812, µPD780814, µPD78F0818 6.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a RC-resonator (standard: 40kHz) connected to the CL1 and CL2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the CL1 pin and open the CL2 pin.
Page 102 µPD780812, µPD780814, µPD78F0818 Figure 6-5: Examples of Oscillator with Bad Connection (1/3) (a) Wiring of connection (b) A signal line crosses over circuits is too long oscillation circuit lines PORTn (n = 0, 2, 4 to 7) Remark: When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert resistors in series on the side of XT2.
Page 103: When No Subsystem Clocks Are Used
µPD780812, µPD780814, µPD78F0818 Figure 6-5: Examples of Oscillator with Bad Connection (3/3) Signals are fetched (f) Signal conductors of the main and sub- system clock are parallel and near each other CL1 and CL2 are wiring in parallel Remark: When using a subsystem clock, replace X1 and X2 with CL1 and CL2, respectively. Caution: In Figure 6-5 (f), CL1 and X1 are wired in parallel.
Page 104: Clock Generator Operations
µPD780812, µPD780814, µPD78F0818 6.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f • Subsystem clock f • CPU clock f •...
Page 105: Main System Clock Operations
µPD780812, µPD780814, µPD78F0818 6.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.
Page 106: Subsystem Clock Operations
µPD780812, µPD780814, µPD78F0818 Figure 6-6: Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 6.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out.
Page 107: Changing System Clock And Cpu Clock Settings
µPD780812, µPD780814, µPD78F0818 Changing System Clock and CPU Clock Settings 6.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bit 0 to bit 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC).
Page 108: System Clock And Cpu Clock Switching Procedure
µPD780812, µPD780814, µPD78F0818 6.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 6-7: System Clock and CPU Clock Switching RESET Interrupt Request Signal SystemClock CPUClock Minimum Maximum Speed Subsystem Clock High-Speed Speed Operation...
Page 109 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 110: Chapter 7 Main Clock Monitor
µPD780812, µPD780814, µPD78F0818 Chapter 7 Main Clock Monitor 7.1 Main Clock Monitor Function The main clock monitor task is, to watch the activities of the main system clock by using the subsystem clock. If the main clock fails for more than three sub clock cycles, the main clock monitor detects the fault condition and triggers the chip reset.
Page 111: Main Clock Monitor Control Register
µPD780812, µPD780814, µPD78F0818 7.3 Main Clock Monitor Control Register The following register is used to control the main clock monitor. • Clock monitor mode register. (1) Clock monitor mode register (CLM) This register endes the main clock monitor. CLM is set with an 1-bit or an 8-bit memory manipulation instruction. RESET input sets CLM to 00H.
Page 112 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 113: Chapter 8 16-Bit Timer/Counter Tm0
µPD780812, µPD780814, µPD78F0818 Chapter 8 16-Bit Timer/Counter TM0 8.1 16-bit Timer/Event Counter Function 16-bit timer/event counter (TM0) has the following functions: • Interval timer • PPG output • Pulse width measurement • External event counter • Square wave output • One-shot pulse output (1) Interval timer When 16-bit timer/event counter is used as an interval timer, it generates an interrupt request at predetermined time intervals.
Page 114: 16-Bit Timer/Event Counter Configuration
µPD780812, µPD780814, µPD78F0818 8.2 16-bit Timer/Event Counter Configuration 16-bit timer/event counter (TM0) consists of the following hardware: Table 8-1: Configuration of 16-bit Timer/Event Counter (TM0) Item Configuration Timer register 16 bits x 1 (TM0) Capture/compare register: 16 bits x 2 (CR00, Register CR01) Timer output...
Page 115 µPD780812, µPD780814, µPD78F0818 1) 16-bit timer register (TM0) TM0 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of an input clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read.
Page 116: Valid Edge Of Ti00 Pin And Valid Edge Of Capture Trigger Of Capture/Compare Register
µPD780812, µPD780814, µPD78F0818 2) Capture/compare register 00 (CR00) CR00 is a 16-bit register that functions as a capture register and as a compare register. Whether this register functions as a capture or compare register is specified by using bit 0 (CRC00) of the capture/compare control register 0.
Page 117 µPD780812, µPD780814, µPD78F0818 (3) Capture/compare register 01 (CR01) This is a 16-bit register that can be used as a capture register and a compare register. Whether it is used as a capture register or compare register is specified by bit 2 (CRC02) of the capture/compare control register 0.
Page 118: 16-Bit Timer/Event Counter Control Register
µPD780812, µPD780814, µPD78F0818 16-Bit Timer/Event Counter Control Register The following four types of registers control 16-bit timer/event counter (TM0). • 16-bit timer mode control register (TMC0) • Capture/compare control register (CRC0) • 16-bit timer output control register (TOC0) • Prescaler mode register 0 (PRM0) •...
Page 119 µPD780812, µPD780814, µPD78F0818 Figure 8-2: Format of 16-Bit Timer Mode Control Register (TMC0) Address: FF60H After Reset: 00H Symbol TMC0 TMC03 TMC02 TMC01 OVF0 Operating Mode Selection of TO0 Generation of TMC03 TMC02 TMC01 Clear mode and output timing interrupt clear mode Operation stop Not affected...
Page 120 µPD780812, µPD780814, µPD78F0818 Cautions 1. Before changing the clear mode and TO0 output timing, be sure to stop the timer operation (reset TMC02 and TMC03 to 0, 0). 2. The valid edge of the TI00 pin is selected by using the prescaler mode register 0 (PRM0).
Page 121 µPD780812, µPD780814, µPD78F0818 (2) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers (CR00 and CR01). CRC0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 to 00H. Figure 8-3: Format of Capture/Compare Control Register 0 (CRC0) Address: FF62H After Reset: 04H Symbol...
Page 122 µPD780812, µPD780814, µPD78F0818 (3) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter (TM0) output control circuit by setting or resetting the R-S flip-flop, enabling or disabling reverse output, enabling or disabling output of 16-bit timer/counter (TM0), enabling or disabling one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software.
Page 123 µPD780812, µPD780814, µPD78F0818 (4) Prescaler mode register 0 (PRM0) This register selects a count clock of the 16-bit timer/event counter (TM0) and the valid edge of TI00, TI01 input. PRM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PRM0 to 00H.
Page 124 µPD780812, µPD780814, µPD78F0818 (5) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P70/TO0/TI00 pin for timer output, set PM70 and the output latch of P70 to 0. PM7 is set with an 1-bit or 8-bit memory manipulation instruction. RESET input sets PM0 value to FFH.
Page 125: 16-Bit Timer/Event Counter Operations
µPD780812, µPD780814, µPD78F0818 16-Bit Timer/Event Counter Operations 8.4.1 Operation as interval timer (16 bits) The 16-bit timer/event counter operates as an interval timer when the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) are set as shown in Figure 8-7. In this case, 16-bit timer/event counter repeatedly generates an interrupt at the time interval specified by the count value set in advance to the 16-bit capture/compare register 00 (CR00).
Page 126 µPD780812, µPD780814, µPD78F0818 Figure 8-8: Configuration of Interval Timer 16-bit capture/compare register 00 (CR00) INTTM00 fx/2 fx/2 fx/2 OVF0 16-bit timer register (TM0) TI01/P71 Clear circuit Figure 8-9: Timing of Interval Timer Operation Count clock TM0 count value 0000H 0001H 0000H 0001H 0000H 0001H Count starts...
Page 127: Ppg Output Operation
µPD780812, µPD780814, µPD78F0818 8.4.2 PPG output operation The 16-bit timer/counter can be used for PPG (Programmable Pulse Generator) output by setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10. The PPG output function outputs a rectangular wave with a cycle specified by the count value set in advance to the 16-bit capture/compare register 00 (CR00) and a pulse width specified by the count value set in advance to the 16-bit capture/compare register 01 (CR01).
Page 128: Pulse Width Measurement
µPD780812, µPD780814, µPD78F0818 8.4.3 Pulse width measurement The 16-bit timer register (TM0) can be used to measure the pulse widths of the signals input to the TI00 and TI01 pins. Measurement can be carried out with TM0 used as a free running counter or by restarting the timer in synchronization with the edge of the signal input to the TI00 pin.
Page 129 µPD780812, µPD780814, µPD78F0818 Figure 8-12: Configuration for Pulse Width Measurement with Free Running Counter fx/2 OVF0 fx/2 16-bit timer register (TM0) fx/2 16-bit capture/compare register 01 TI00/P70 (CR01) INTTM00 Internal bus Figure 8-13: Timing of Pulse Width Measurement with Free Running Counter and One Capture Register (with both edges specified) Count clock TM0 count value...
Page 130 µPD780812, µPD780814, µPD78F0818 (2) Measurement of two pulse widths with free running counter The pulse widths of the two signals respectively input to the TI00 and TI01 pins can be measured when the 16-bit timer register (TM0) is used as a free running counter (refer to Figure 8-14). When the edge specified by bits 4 and 5 (ES00 and ES01) of the prescaler mode register 0 (PRM0) is input to the TI00 pin, the value of the TM0 is loaded to the 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTTM01) is set.
Page 131 µPD780812, µPD780814, µPD78F0818 • Capture operation (free running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 8-15: CR01 Capture Operation with Rising Edge Specified Count clock TM50 N N+1 FFH 00H N 00H 01H TM51 CR50...
Page 132 µPD780812, µPD780814, µPD78F0818 (3) Pulse width measurement with free running counter and two capture registers When the 16-bit timer register (TM0) is used as a free running counter (refer to Figure 8-17), the pulse width of the signal input to the TI00 pin can be measured. When the edge specified by bits 4 and 5 (ES00 and ES01) of the prescaler mode register 0 (PRM0) is input to the TI00 pin, the value of TM0 is loaded to the 16-bit capture/compare register 01 (CR01), and an external interrupt request signal (INTTM01) is set.
Page 133 µPD780812, µPD780814, µPD78F0818 Figure 8-18: Timing of Pulse Width Measurement with Free Running Counter and Two Capture Registers (with rising edge specified) Count clock TM0 count value 0000H 0001H FFFFH 0000H TI00 pin input Value loaded to CR01 Value loaded to CR00 INTTM01 OVF0...
Page 134 µPD780812, µPD780814, µPD78F0818 (4) Pulse width measurement by restarting When the valid edge of the TI00 pin is detected, the pulse width of the signal input to the TI00n pin can be measured by clearing the 16-bit timer register (TM0) once and then resuming counting after loading the count value of TM0 to the 16-bit capture/compare register 01 (CR01).
Page 135: Operation As External Event Counter
µPD780812, µPD780814, µPD78F0818 Figure 8-20: Timing of Pulse Width Measurement by Restarting (with rising edge specified) Count clock TM0 count value 0000H 0001H 0000H 0001H 0001H 0000H TI00 pin input Value loaded to CR01 Value loaded to CR00 INTTM01 D1 x 1 D2 x 1 8.4.4 Operation as external event counter 16-bit timer/event counter can be used as an external event counter which counts the number of clock...
Page 136 µPD780812, µPD780814, µPD78F0818 Figure 8-21: Control Register Settings in External Event Counter Mode (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts on coincidence between TM0 and CR00 (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 137: Operation To Output Square Wave
µPD780812, µPD780814, µPD78F0818 Figure 8-23: Timing of External Event Counter Operation (with rising edge specified) TI00 pin input TM0 count value 0000H 0001H 0002H 0003H 0004H 0005H N - 1 0000H 0001H 0002H 0003H CR00 INTTM00 Caution: Read TM0 when reading the count value of the external event counter. 8.4.5 Operation to output square wave The 16-bit timer/event counter can be used to output a square wave with any frequency at an interval specified by the count value set in advance to the 16-bit capture/compare register 00 (CR00).
Page 138 µPD780812, µPD780814, µPD78F0818 Figure 8-24: Set Contents of Control Registers in Square Wave Output Mode (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts on coincidence between TM0 and CR00. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 139: Operation To Output One-Shot Pulse
µPD780812, µPD780814, µPD78F0818 8.4.6 Operation to output one-shot pulse 16-bit timer/event counter can output a one-shot pulse in synchronization with a software trigger and an external trigger (TI00/TO0/P70 pin input). (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO0/P70 pin by setting the 16-bit timer mode control register (TMC0), capture/com7-26, and by setting bit 6 (OSPT) of TOC0 by software.
Page 140 µPD780812, µPD780814, µPD78F0818 Figure 8-26: Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts on coincidence between TM0 and CR00 (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 141 µPD780812, µPD780814, µPD78F0818 Figure 8-27: Timing of One-Shot Pulse Output Operation with Software Trigger Sets 0CH to TMC0 (TM0 count starts) Count clock TM0 count value 0000H 0001H N + 1 0000H N - 1 M - 1 0000H 0001H 0002H CR01 set value CR00 set value OSPT...
Page 142 µPD780812, µPD780814, µPD78F0818 Figure 8-28: Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts at valid edge of TI00/TO0/P70 pin (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 143 µPD780812, µPD780814, µPD78F0818 Figure 8-29: Timing of One-Shot Pulse Output Operation with External Trigger (with rising edge specified) Sets 08H to TMC0 (TM0 count starts) Count clock TM0 count value 0000 0001 0000 M+2 M+3 CR01 set value CR00 set value TI00 pin input INTTM01 INTTM00...
Page 144: 16-Bit Timer/Event Counter Operating Precautions
µPD780812, µPD780814, µPD78F0818 8.5 16-Bit Timer/Event Counter Operating Precautions (1) Error on starting timer An error of up to 1 clock occurs before the coincidence signal is generated after the timer has been started. This is because the 16-bit timer register (TM0) is started asynchronously in respect to the count pulse. Figure 8-30: Start Timing of 16-Bit Timer Register Count pulses 0000H...
Page 145 µPD780812, µPD780814, µPD78F0818 (4) Data hold timing of capture register If the valid edge is input to the TI00 pin while the 16-bit capture/compare register 01 (CR01) is read, CR01 performs the capture operation, but this capture value is not guaranteed. However, the interrupt request flag (INTTM01) is set as a result of detection of the valid edge.
Page 146 µPD780812, µPD780814, µPD78F0818 7) Operation of OVF0 flag The OVF0 flag is set to 1 in the following case: Select mode in which 16-bit timer/counter is cleared and started on coincidence between TM0 and CR00. ↓ Set CR00 to FFFFH ↓...
Page 147 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 148: Chapter 9 16-Bit Timer 2 Tm2
µPD780812, µPD780814, µPD78F0818 Chapter 9 16-Bit Timer 2 TM2 9.1 16-Bit Timer 2 Functions The 16-bit timer 2 (TM2) has the following functions. • Pulse width measurement • Divided output of input pulse • Time stamp function for the DCAN Figure 9-1 shows 16-Bit Timer 2 Block Diagram.
Page 149: 16-Bit Timer 2 Configuration
µPD780812, µPD780814, µPD78F0818 9.2 16-Bit Timer 2 Configuration Timer 2 consists of the following hardware. Table 9-1: Timer 2 Configuration Item Configuration Timer register 16 bits x 1 (TM2) Register Capture register: 16 bits x 3 (CR20 to CR22) 16 bit timer mode control register (TMC2) Control register Capture pulse control register (CRC2) Prescaler mode register (PRM2)
Page 150: 16-Bit Timer 2 Control Registers
µPD780812, µPD780814, µPD78F0818 9.3 16-Bit Timer 2 Control Registers The following three types of registers are used to control timer 0. • 16-bit timer mode control register (TMC2) • Capture pulse control register (CRC2) • Prescaler mode register (PRM2) (1) 16-bit timer mode control register (TMC2) This register sets the 16-bit timer operating mode and controls the prescaler output signals.
Page 151 µPD780812, µPD780814, µPD78F0818 (2) Capture pulse control register (CRC2) This register specifies the division ratio of the capture pulse input to the 16-bit capture register (CR22) from an external source. CRC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC2 value to 04H.
Page 152 µPD780812, µPD780814, µPD78F0818 (3) Prescaler mode register (PRM2) This register is used to set 16-bit timer (TM2) count clock and valid edge of TI2n (n = 0 to 2) input. PRM2 is set with an 8-bit memory manipulation instruction. RESET input sets PRM2 value to 00H. Figure 9-4: Prescaler Mode Register (PRM2) Format Symbol Address...
Page 153: 16-Bit Timer 2 Operations
µPD780812, µPD780814, µPD78F0818 16-Bit Timer 2 Operations 9.4.1 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI20/P60 to TI22/P62 pins by using the 16-bit timer register (TM2). TM2 is used in free-running mode. (1) Pulse width measurement with free-running counter and one capture register (TI20) When the edge specified by the prescaler mode register (PRM2) is input to the TI20/P60 pin, the value of TM2 is taken into 16-bit capture register 20 (CR20) and an external interrupt request signal...
Page 154 µPD780812, µPD780814, µPD78F0818 (2) Measurement of three pulse widths with the free running counter The 16-bit timer register (TM2) allows simultaneous measurement of the pulse widths of the three signals input to the TI20/P60 to TI22/P62 pins. When the edge specified by bits 2 and 3 (ES00 and ES01) of prescaler mode register (PRM2) is input to the TI20/P60 pin, the value of TM2 is taken into 16-bit capture register 20 (CR20) and an external interrupt request signal (INTTM20) is set.
Page 155 µPD780812, µPD780814, µPD78F0818 Figure 9-8: Timing of Pulse Width Measurement Operation by Free Running Counter (with Both Edges Specified) Count clock TM2 count value 0000H 0001H FFFFH 0000H TI2m pin input Value loaded to CR2m INTTM2m TI2n pin input Value loaded to CR2n INTTM2n INTOVF (D1 –...
Page 156: 16-Bit Timer 2 Precautions
µPD780812, µPD780814, µPD78F0818 9.5 16-Bit Timer 2 Precautions (1) Timer start errors An error with a maximum of one clock may occur until counting is started after timer start, because the 16-bit timer register (TM2) is started asynchronously with the count pulse. Figure 9-9: 16-Bit Timer Register Start Timing Count pulse 0000H...
Page 157 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 158: Chapter 10 8-Bit Timer/Event Counters 50 And 51
µPD780812, µPD780814, µPD78F0818 Chapter 10 8-Bit Timer/Event Counters 50 and 51 10.1 8-Bit Timer/Event Counters 50 and 51 Functions The timer 50 and 51 have the following two modes: - Mode using TM50 and TM51 alone (individual mode) - Mode using the cascade connection ( 16-bit cascade mode connection ). (1) Mode using TM50 and TM51 alone The timer operate as 8-bit timer/event counters.
Page 159: 8-Bit Operation Modes
µPD780812, µPD780814, µPD78F0818 10.1.1 8-Bit Operation Modes (1) Interval timer Interrupts are generated at the preset time intervals. Table 10-1: 8-Bit Timer/Event Counter 50 Interval Times Minimum Interval Width Maximum Interval Width Resolution (125 ns) x 1/f (32 µs) (125 ns) x 1/f (250 ns) x 1/f...
Page 160: 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges
µPD780812, µPD780814, µPD78F0818 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 10-3: 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution...
Page 161: 16-Bit Operation Modes
µPD780812, µPD780814, µPD78F0818 10.1.2 16-Bit Operation Modes (1) Interval timer Interrupts are generated at the present interval time. Table 10-5: 16-Bit Timer/Event Counter TM50/TM51 Interval Times Minimum Interval Width Maximum Interval Width Resolution (125 ns) x 1/f (8,2 ms) (125 ns) x 1/f (250 ns) x 1/f...
Page 162: 8-Bit Timer/Event Counters 50 And 51 Configurations
µPD780812, µPD780814, µPD78F0818 10.2 8-Bit Timer/Event Counters 50 and 51 Configurations The 8-bit timer/event counters 50 and 51 consist of the following hardware. Table 10-7: 8-Bit Timer/Event Counters 50 and 51 Configurations Item Configuration Timer register 8 bits x 2 (TM50, TM51) Register Compare register 8 bits x 2 (CR50, CR51) Timer output...
Page 163 µPD780812, µPD780814, µPD78F0818 Figure 10-2: 8-Bit Timer/Event Counter 51 (TM51) Block Diagram Internal Bus 8-Bit Compare Register 51 INTTM51 Selector (CR51) TI51 Match 8-Bit Counter 51 TO51 (TM51) Clear Level Inversion Selector TCL512 TCL511 TCL510 TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51 Timer Clock Select Timer Mode Control Register 51 (TCL51)
Page 164 µPD780812, µPD780814, µPD78F0818 Figure 10-3: Block Diagram of 8-Bit Timer/Event Counters 50 and 51 Output Control Circuit TMCn1 TMCn6 RESET LVRn LVSn TO50/P26/TI50, TO51/P27/TI51 TMCn1 PM26, P26, P27 TMCn6 PM27 Output Latch INTTMn PWM Output Circuit Timer Output F/F2 TCEn INTTMn Level OVFn...
Page 165: 8-Bit Timer/Event Counters 50 And 51 Control Registers
µPD780812, µPD780814, µPD78F0818 10.3 8-Bit Timer/Event Counters 50 and 51 Control Registers The following three types of registers are used to control the 8-bit timer/event counters 50 and 51. • Timer clock select register 50 and 51 (TCL50, TCL51) • 8-bit timer mode control registers 50 and 51 (TMC50, TMC51) •...
Page 166 µPD780812, µPD780814, µPD78F0818 (2) Timer clock select register 51 (TCL51) This register sets count clocks of 8-bit timer register 51. TCL51 is set with an 8-bit memory manipulation instruction. RESET input sets TCL51 to 00H. Figure 10-5: Timer Clock Select Register 51 Format Address After Reset Symbol...
Page 167 µPD780812, µPD780814, µPD78F0818 (3) 8-bit timer mode control register 50 (TMC50) This register enables/stops operation of 8-bit timer register 50, sets the operating mode of 8-bit timer register 50 and controls operation of 8-bit timer/event counter 50 output control circuit. It selects the R-S flip-flop (timer output F/F 1,2) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other than PWM mode and 8-bit timer/event counter 5 timer output enabling/ disabling.
Page 168 µPD780812, µPD780814, µPD78F0818 (4) 8-bit timer mode control register 51 (TMC51) This register enables/stops operation of 8-bit timer register 51, sets the operating mode of 8-bit timer register 51 and controls operation of 8-bit timer/event counter 51 output control circuit. It selects the R-S flip-flop (timer output F/F 1,2) setting/resetting, active level in PWM mode, inversion enabling/disabling in modes other than PWM mode and 8-bit timer/event counter 51 timer output enabling/ disabling.
Page 169 µPD780812, µPD780814, µPD78F0818 (5) Port mode register 2 (PM2) This register sets port 2 input/output in 1-bit units. When using the P26/TI50/TO50 and P27/TI51/TO51 pins for timer output, set PM26, PM27 and output latches of P26 and P27 to 0. PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 170: 8-Bit Timer/Event Counters 50 And 51 Operations
µPD780812, µPD780814, µPD78F0818 10.4 8-Bit Timer/Event Counters 50 and 51 Operations 10.4.1 Interval timer operations (8-Bit Timer/Event Counter Mode) Setting the 8-bit timer mode control registers (TMC50 and TMC51) as shown in Figure 10-9 allows operation as an interval timer. Interrupts are generated repeatedly using the count value preset in 8-bit compare registers (CR50 and CR51) as the interval.
Page 171 µPD780812, µPD780814, µPD78F0818 Figure 10-10: Interval Timer Operation Timings (1/2) (a) When N = 00H to FFH Count Clock TMn Count Value Clear Clear TCEn Count Start INTTMn Interrupt Acknowledge Interrupt Acknowledge Interval Time Interval Time Interval Time Remarks: 1. Interval time = (N + 1) x t: N = 00H to FFH 2.
Page 172 µPD780812, µPD780814, µPD78F0818 Figure 10-10: Interval Timer Operation Timings (2/2) (c) When CRn = FFH Count clock TCEn INTTMn Interrupt received Interrupt received TIOn Interval time Remark: n = 50, 51 (d) Operated by CR5n transition (M < N) Count clock TCEn INTTMn TIOn...
Page 173: 8-Bit Timer/Event Counter 50 Interval Times (8-Bit Timer/Event Counter Mode)
µPD780812, µPD780814, µPD78F0818 Table 10-8: 8-Bit Timer/Event Counters 50 Interval Times (8-Bit Timer/Event Counter Mode) Minimum Interval Maximum Interval TCL502 TCL501 TCL500 Resolution Time Time Tin input edge input Tin input cycle x Tin input cycle cycle Tin input edge input Tin input cycle x Tin input cycle cycle...
Page 174: External Event Counter Operation
µPD780812, µPD780814, µPD78F0818 10.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI50/P06/TO50 and TI51/P27/TO51 pins with 8-bit timer registers 50 and 51 (TM50 and TM51). TM50 and TM51 are incremented each time the valid edge specified with timer clock select registers 50 and 51 (TCL50 and TCL51) is input.
Page 175: Square Wave Output
µPD780812, µPD780814, µPD78F0818 10.4.3 Square-wave output A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers (CR50 and CR51). The TO50/P26/TI50 or TO51/P27/TI51 pin output status is reversed at intervals of the count value preset to CR50 or CR51 by setting bit 1 (TMC501) and bit 0 (TOE50) of the 8-bit timer output control register 5 (TMC50), or bit 1 (TMC511) and bit 0 (TOE51) of the 8-bit timer mode control register 6 (TMC51) to 1.
Page 176: 8-Bit Timer/Event Counters 50 Square-Wave Output Ranges (8-Bit Timer/Event Counter Mode)
µPD780812, µPD780814, µPD78F0818 Figure 10-14: Square-wave Output Operation Timing Count clock TMn count value Count start Note Note: TOn output initial value can be set by bits 2 and 3 (LVRn, LVSn) of the 8-bit timer mode control register TCMn. Remark: n = 50, 51 Table 10-10: 8-Bit Timer/Event Counters 50 Square-Wave Output Ranges...
Page 177: Pwm Output Operations
µPD780812, µPD780814, µPD78F0818 10.4.4 PWM output operations Setting the 8-bit timer mode control registers (TMC50 and TMC51) as shown in Figure 10-15 allows operation as PWM output. Pulses with the duty rate determined by the values preset in 8-bit compare registers (CR50 and CR51) output from the TO50/P26/TI50 or TO51/P27/TI51 pin.
Page 178 µPD780812, µPD780814, µPD78F0818 Figure 10-16: PWM Output Operation Timing (Active high setting) CRn Changing Count Clock N+3 00 TMn Count Value TCEn INTTMn OVFn Inactive Level Inactive Level Active Level Inactive Level Remark: n = 50, 51 Figure 10-17: PWM Output Operation Timings (CRn0 = 00H, active high setting) CRn Changing Count Clock TMn Count Value...
Page 179 µPD780812, µPD780814, µPD78F0818 Figure 10-18: PWM Output Operation Timings (CRn = FFH, active high setting) Count Clock TMn Count Value TCEn INTTMn OVFn Inactive Level Inactive Level Active Level Inactive Level Active Level Remark: n = 50, 51 Figure 10-19: PWM Output Operation Timings (CRn changing, active high setting) CRn Changing Count Clock...
Page 180: Operation As Interval Timer (16-Bit Operation)
µPD780812, µPD780814, µPD78F0818 10.5 Operation as interval timer (16-bit operation) (1) Cascade (16-bit timer) mode (TM50 and TM51) The 16-bit resolution timer/counter mode is set by setting bit 4 (TMC514) of the 8-bit timer mode control register 51 (TMC51) to “1”. In this mode, TM50 and TM51 operate as a 16-bit interval timer that repeatedly generates an interrupt request at intervals specified by the count value set in advance to 8-bit compare registers 50 and 51 (CR50 and CR51).
Page 181 µPD780812, µPD780814, µPD78F0818 Figure 10-21 shows an example of timing in the 16-bit resolution cascade mode. Figure 10-21: 16-Bit Resolution Cascade Mode (with TM50 and TM51) Count clock TM50 FFH 00H 00H 01H TM51 CR50 CR51 TCE50 TCE51 INTTM50 Interval time TO50 Interrupt request Operation...
Page 182 µPD780812, µPD780814, µPD78F0818 Table 10-12: 8-Bit Timer/Event Counters Interval Times (16-Bit Timer/Event Counter Mode) TCL502 TCL501 TCL500 Minimum Interval Time Maximum Interval Time Resolution TI50 input cycle x TIn input cycle TIn input cycle TI50 input cycle x TIn input cycle TIn input cycle (125 ns) x 1/f...
Page 183: Cautions On 8-Bit Timer/Event Counters 50 And 51
µPD780812, µPD780814, µPD78F0818 10.6 Cautions on 8-Bit Timer/Event Counters 50 and 51 (1) Timer start errors An error with a maximum of one clock might occur concerning the time required for a match signal to be generated after the timer starts. This is because 8-bit timer registers 50 and 51 are started asynchronously with the count pulse.
Page 184 µPD780812, µPD780814, µPD78F0818 (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers (CR50 and CR51) are changed are smaller than those of 8-bit timer registers (TM50 and TM51), TM50 and TM51 continue counting, overflow and then restarts counting from 0.
Page 185 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 186: Chapter 11 Watch Timer
µPD780812, µPD780814, µPD78F0818 Chapter 11 Watch Timer 11.1 Watch Timer Functions The watch timer has the following functions: • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. The figure 11-1 shows Watch Timer Block Diagram. Figure 11-1: Block Diagram of Watch Timer Clear 5-bit counter...
Page 187: Watch Timer Configuration
µPD780812, µPD780814, µPD78F0818 (1) Watch timer When the main system clock or subsystem clock is used, interrupt requests (INTWT) are generated at the following time intervals. Table 11-1: Watch Timer Interval Time Watch Timer When operated at When operated at When operated at Interval Time fx = 8.00 MHz...
Page 188: Watch Timer Mode Register (Wtm)
µPD780812, µPD780814, µPD78F0818 11.3 Watch Timer Mode Register (WTM) This register sets the watch timer count clock, the watch timer operating mode, and prescaler interval time and enables/disables prescaler and 5-bit counter operations. WTM is set with a 1-bit or 8-bit memory manipulation instruction.
Page 189: Watch Timer Operations
µPD780812, µPD780814, µPD78F0818 11.4 Watch Timer Operations 11.4.1 Watch timer operation The watch timer operates as internal timer and generates interrupt requests repeatedly at a defined interval. When the 32,768 kHz subsystem clock is used, the watch timer generates also 0,25 -second and 0,5-second intervals which can be used for clocks etc.
Page 190 µPD780812, µPD780814, µPD78F0818 Figure 11-3: Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock f Watch timer interrupt INTWT Interrupt time of watch timer Interrupt time of watch timer Interval timer interrupt INTWTI Interval timer Remark: : Watch timer clock frequency...
Page 191 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 192: Chapter 12 Watchdog Timer
µPD780812, µPD780814, µPD78F0818 Chapter 12 Watchdog Timer 12.1 Watchdog Timer Functions The watchdog timer has the following functions: • Watchdog timer • Interval timer Caution: Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM). (1) Watchdog timer mode An inadvertent program loop is detected.
Page 193: Watchdog Timer Configuration
µPD780812, µPD780814, µPD78F0818 12.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 12-3: Watchdog Timer Configuration Item Configuration Timer clock select register (WDCS) Control register Watchdog timer mode register (WDTM) Figure 12-1: Watchdog Timer Block Diagram Internal Bus Prescaler TMMK4...
Page 194: Watchdog Timer Control Registers
µPD780812, µPD780814, µPD78F0818 12.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Watchdog timer clock select register (WDCS) • Watchdog timer mode register (WDTM) (1) Watchdog timer clock select register (WDCS) This register sets the watchdog timer count clock.
Page 195 µPD780812, µPD780814, µPD78F0818 (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 12-3: Watchdog Timer Mode Register Format Symbol Address AfterReset...
Page 196: Watchdog Timer Operations
µPD780812, µPD780814, µPD78F0818 12.4 Watchdog Timer Operations 12.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (WDCS0 to WDCS2) of the timer clock select register (WDCS).
Page 197: Interval Timer Operation
µPD780812, µPD780814, µPD78F0818 12.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupts repeatedly at an interval of the preset count value when bit 3 (WDTM3) of the watchdog timer mode register (WDTM) is set to 0, respectively.
Page 198 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 199: Chapter 13 Clock Output Control Circuit
µPD780812, µPD780814, µPD78F0818 Chapter 13 Clock Output Control Circuit 13.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the clock output selection register (CKS) are output from the PCL/P23 pin.
Page 200: Clock Output Control Circuit Configuration
µPD780812, µPD780814, µPD78F0818 13.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 13-1: Clock Output Control Circuit Configuration Item Configuration Clock output selection register (CKS) Control register Port mode register 3 (PM3) Figure 13-2: Clock Output Control Circuit Block Diagram Synchronizing Circuit...
Page 201: Clock Output Function Control Registers
µPD780812, µPD780814, µPD78F0818 13.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Clock output selection register (CKS) • Port mode register 2 (PM2) (1) Clock output selection register (CKS) This register sets PCL output clock.
Page 202 µPD780812, µPD780814, µPD78F0818 2) Port mode register 2 (PM2) This register set port 3 input/output in 1-bit units. When using the P23/PCL pin for clock output function, set PM23 and output latch of P23 to 0. PM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH.
Page 203 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 204: Chapter 14 A/D Converter
µPD780812, µPD780814, µPD78F0818 Chapter 14 A/D Converter 14.1 A/D Converter Functions The A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It can control up to 12 analog input channels (ANI0 to ANI11). This A/D converter has the following functions: (1) A/D conversion with 8-bit resolution One channel of analog input is selected from ANI0 to ANI11, and A/D conversion is repeatedly executed with a resolution of 8 bits.
Page 205: A/D Converter Configuration
µPD780812, µPD780814, µPD78F0818 Figure 14-2: Power-Fail Detection Function Block Diagram ANI0/P10 PFCM PFEN ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 INTAD ANI5/P15 A/D converter Comparator ANI6/P16 ANI7/P17 ANI8 Power-fail compare ANI9 threshold value ANI10 PFEN PFCM register (PFT) ANI11 Power-fail compare mode register (PFM) Internal bus 14.2 A/D Converter Configuration A/D converter consists of the following hardware.
Page 206 µPD780812, µPD780814, µPD78F0818 (3) Sample & hold circuit The sample & hold circuit samples each analog input sequentially applied from the input circuit, and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion.
Page 207: A/D Converter Control Registers
µPD780812, µPD780814, µPD78F0818 14.3 A/D Converter Control Registers The following 4 types of registers are used to control A/D converter. • A/D converter mode register (ADM1) • Analog input channel specification register (ADS1) • Power-fail compare mode register (PFM) • Power-fail compare threshold value register (PFT) (1) A/D converter mode register (ADM1) This register sets the conversion time for analog input to be A/D converted, conversion start/stop and external trigger.
Page 208 µPD780812, µPD780814, µPD78F0818 (2) Analog input channel specification register (ADS1) This register specifies the analog voltage input port for A/D conversion. ADS1 is set with an 8-bit memory manipulation instruction. RESET input clears ADS1 to 00H. Figure 14-4: Analog Input Channel Specification Register (ADS1) Format Symbol Address After Reset R/W...
Page 209 µPD780812, µPD780814, µPD78F0818 (3) Power-fail compare mode register (PFM) The power-fail compare mode register (PFM) controls a comparison operation. RESET input clears PFM to 00H. Figure 14-5: Power-Fail Compare Mode Register (PFM) Format Symbol Address After Reset R/W PFEN PFCM FF9AH PFEN Enables Power-Fail Comparison...
Page 210: A/D Converter Operations
µPD780812, µPD780814, µPD78F0818 14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with the analog input channel specification register (ADS1). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
Page 211 µPD780812, µPD780814, µPD78F0818 Figure 14-7: Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR1 result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS1) of the A/D converter mode register (ADM1) is reset (to 0) by software.
Page 212: Input Voltage And Conversion Result
µPD780812, µPD780814, µPD78F0818 14.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (stored in the A/D conversion result register (ADCR1)) is shown by the following expression.
Page 213: A/D Converter Operation Mode
µPD780812, µPD780814, µPD78F0818 14.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One analog input channel is selected from among ANI0 to ANI11 with the analog input channel specification register (ADS1) and A/D conversion is performed.
Page 214 µPD780812, µPD780814, µPD78F0818 Figure 14-9: A/D Conversion ADM1 rewrite ADCS1 = 1 ADS1 rewrite ADCS1 = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion suspended; Stop Conversion results are not stored ADCR1 ANIn ANIn ANIm INTAD (PFEN = 0) INTAD (PFEN = 1) First conversion Condition satisfied...
Page 215: A/D Converter Precautions
µPD780812, µPD780814, µPD78F0818 14.5 A/D Converter Precautions (1) Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by setting bit 7 (ADCS1) of the A/D converter mode register (ADM1) to 0 to stop conversion. Figure 14-10 shows how to reduce the current consumption in the standby mode.
Page 216 µPD780812, µPD780814, µPD78F0818 (4) Noise countermeasures To maintain 8-bit resolution, attention must be paid to noise input to pin AV and pins ANI0 to ANI11. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 14-11 to reduce noise.
Page 217 µPD780812, µPD780814, µPD78F0818 (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS1) is changed. Caution is therefore required if a change of analog input pin is performed during A/D conversion. The A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS1 rewrite, if the ADIF is read immediately after the ADS1 rewrite, the ADIF may be set despite to the fact that the A/D conversion for the post-change analog input...
Page 218: Cautions On Emulation
µPD780812, µPD780814, µPD78F0818 14.6 Cautions on Emulation To perform debugging with an in-circuit emulator (IE-78001-R-A), the D/A converter mode register (DAM0) must be set. DAM0 is a register used to set the I/O board (IE-78K0-NS-P04). 14.6.1 D/A converter mode register (DAM0) DAM0 is necessary if the power-fail detection function is used.
Page 219 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 220: Chapter 15 Serial Interface Outline
µPD780812, µPD780814, µPD78F0818 Chapter 15 Serial Interface Outline 15.1 Serial Interface Outline The µPD780814 subseries incorporates two channels of serial interfaces. Table 15-1: Differences between the Serial Interface Channels Serial Transfer Mode µPD780812 µPD780814 µPD78F0818 ‰ ‰ ‰ SIO 0 (3-wire serial I/O) ‰...
Page 221 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 222: Chapter 16 Serial Interface Channel 20
µPD780812, µPD780814, µPD78F0818 Chapter 16 Serial Interface Channel 20 16.1 Serial Interface Channel 20 Functions The SIO20 has the following three modes. • Operation stop mode • 3-wire serial I/O mode (standard mode) • 3-wire serial I/O mode (SPI compatible mode) Features: 8-bit data length Simultaneous transmit and receive available...
Page 223 µPD780812, µPD780814, µPD78F0818 Figure 16-1: Block diagram of SIO20 Receive data buffer Direction control register (SIRB20) Receive data circuit buffer status SDVA SDOF register SI/P20 Serial I/O shift register (SIO20) SO/P21 Interrupt request SCK/P22 Serial clock counter INTCSI0 signal generator fx/2 Serial clock control Selector...
Page 224: Serial Interface Channel 20 Configuration
µPD780812, µPD780814, µPD78F0818 16.2 Serial Interface Channel 20 Configuration The SIO20 includes the following hardware. Table 16-1: Configuration of SIO20 Item Configuration Serial I/O shift register (SIO20) Registers Serial I/F receive data buffer (SIRB20) Serial I/F operation mode register (CSIM20) Control registers Receive data buffer status register (SRBS20) 1) Serial I/O shift register (SIO20)
Page 225: Serial Interface Channel 20 List Of Sfrs (Special Function Registers)
µPD780812, µPD780814, µPD78F0818 (4) Receive data buffer status register (SRBS20) This 8-bit read only register reflects the status of the serial I/F receive data buffer (SIRB20). It contains two flags indicating that there is unread data in the receive data buffer or that there is an overflow error. SRBS20 can be read with a 1-bit or 8-bit memory manipulation instruction.
Page 226: Serial Interface Control Registers
µPD780812, µPD780814, µPD78F0818 16.4 Serial Interface Control Registers The SIO20 uses the following type of register for control functions. • Serial operation mode register 20 (CSIM20) • Receive data buffer status register 20 (SBRS20) (1) Serial I/F operation mode register 20 (CSIM20) This register is used to enable or disable serial interface channel 3’s serial clock, operation modes, and specific operations.
Page 227 µPD780812, µPD780814, µPD78F0818 The following figure shows the four different communication modes that can be set by the bits CLPO and CLPH. Figure 16-3: Communication Modes CLPO CLPH SI/SO Data...
Page 228 µPD780812, µPD780814, µPD78F0818 (2) Receive data buffer status register (SRBS20) This register reflects that there is unread data in the serial receive data buffer register or that there is in an overflow error. SRBS20 can be read via a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value to 00H.
Page 229: Serial Interface Operations
µPD780812, µPD780814, µPD78F0818 16.5 Operations The SIO20 has the following two operation modes. • Operation stop mode • 3-wire serial I/O mode 16.5.1 Operation Stop Mode This mode does not perform serial transfers and can therefore reduce power consumption. In operation stop mode the pins connected to SCK, SI and SO can be used for port functions. (1) Register settings Operation stop mode is set via serial operation mode register 20 (CSIM20).
Page 230: 3-Wire Serial I/O Mode
µPD780812, µPD780814, µPD78F0818 16.5.2 3-wire Serial I/O Mode 3-wire serial I/O mode is useful when connecting to a peripheral I/O device that includes a clock-synchronous serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK), serial output line (SO) and serial input line (SI).
Page 231 µPD780812, µPD780814, µPD78F0818 The following figure shows the four different communication modes that can be set by the bits CLPO and CLPH. Figure 16-8: Communications Modes CLPO CLPH SI/SO Data...
Page 232 µPD780812, µPD780814, µPD78F0818 (2) Receive data buffer status register (SRBS20) This register reflects that there is unread data in the serial receive data buffer register or that there is in an overflow error. SRBS20 can be read via a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value to 00H.
Page 233 µPD780812, µPD780814, µPD78F0818 (4) Transfer start Serial transfer starts when the following two conditions have been satisfied. • Transmit/receive mode When CSIE20 = 1 and MODE0 = 0, transfer starts when writing to SIO20. • Receive-only mode When CSIE20 = 1 and MODE0 = 1, transfer starts when reading from SIO20. Caution: The transfer of the serial interface will not start when the data is written to SIO20 if before CSIE20 bit is set to “1”.
Page 234 µPD780812, µPD780814, µPD78F0818 (6) Transmission formats During a SIO transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line synchronizes shifting and sampling on the two serial data lines. (a) Clock phase and polarity By software any of four combination of serial clock (SCK) phase and polarity can be selected, using two bits in the SIO control register.
Page 235 µPD780812, µPD780814, µPD78F0818 (c) Transmission format when CLPH = ‘1’ Figure 16-12 shows a SIO transmission in which CLPH is set to ‘1’. Two waveforms are shown for SCK one for CLPO = ‘1’ and another one for CLPO = ‘0’. The SO pin is the output from the master and the SI pin is the output from the slave.
Page 236 µPD780812, µPD780814, µPD78F0818 (7) Hardware detectable error condition Overflow error The overflow flag (SDOF) is set if the SIO20 receive data buffer (SIRB20) still contains unread data from a previous transmission when the capture strobe of the LSB of the next transmission occurs (see figure 16-13).
Page 237 µPD780812, µPD780814, µPD78F0818 (8) Operation during standby modes (a) HALT mode operation The SIO remains active after the execution of a HALT instruction. In Halt mode the SIO20 module registers are not accessible by the CPU. If the INTCSI interrupt is enabled it can bring the CPU out of HALT mode, if a transmission is completed.
Page 238 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 239: Chapter 17 Serial Interface Uart
µPD780812, µPD780814, µPD78F0818 Chapter 17 Serial Interface UART 17.1 Serial Interface UART Functions The serial interface UART has the following two modes. (1) Operation stop mode This mode is used if the serial transfer is performed to reduce power consumption. For details, see 17.5.1 Operation Stop Mode.
Page 240: Serial Interface Uart Configuration
µPD780812, µPD780814, µPD78F0818 17.2 Serial Interface UART Configuration The UART includes the following hardware. Table 17-1: Configuration of UART Item Configuration Registers Transmit shift register 1 (TXS0) Receive shift register 1 (RX50) Receive buffer register (RXB0) Control registers Asynchronous serial interface mode register (ASIM0) Asynchronous serial interface status register (ASIS0) Baud rate generator control register (BRGC0) (1) Transmit shift register 1 (TXS0)
Page 241: List Of Sfrs (Special Function Registers)
µPD780812, µPD780814, µPD78F0818 17.3 List of SFRS (Special Function Registers) Table 17-2: List of SFRs (Special Function Registers) Units available for bit manipulation SFR name Symbol Value when reset 1 bit 8 bits 16 bits Transmit shift register TXS0 — —...
Page 242 µPD780812, µPD780814, µPD78F0818 Figure 17-2: Format of Asynchronous Serial Interface Mode Register (ASIM0) Address: FFA0H After Reset: 00H Symbol ASIM0 TXE0 RXE0 PS01 PS00 ISRM0 TXE0 RXE0 Operation mode RxD0/P24 pin function TxD0/P25 pin function Operation stop Port function Port function UART0 mode Serial operation Port function...
Page 243 µPD780812, µPD780814, µPD78F0818 (2) Asynchronous serial interface status register (ASIS0) When a receive error occurs during UART mode, this register indicates the type of error. ASIS0 can be read using an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 17-3: Format of Asynchronous Serial Interface Status Register (ASIS0) Address: FFA1H After Reset: 00H Symbol...
Page 244 µPD780812, µPD780814, µPD78F0818 Figure 17-4: Format of Baud Rate Generator Control Register (BRGC0) Address: FFA2H After Reset: 00H Symbol BRGC0 TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00 = 8.00 MHz) TPS02 TPS01 TPS00 Source clock selection for 5-bit counter MDL03 MDL02 MDL01 MDL00...
Page 245: Serial Interface Operations
µPD780812, µPD780814, µPD78F0818 17.5 Serial Interface Operations This section explains the three modes of the UART. 17.5.1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. In the operation stop mode, pins can be used as ordinary ports. (1) Register settings Operation stop mode settings are made via the asynchronous serial interface mode register (ASIM).
Page 246 µPD780812, µPD780814, µPD78F0818 (a) Asynchronous serial interface mode register (ASIM0) ASIM0 can be set by 1-bit or 8-bit memory manipulation instructions. When RESET is input, its value is 00H. Figure 17-6: Asynchronous serial interface mode register (ASIM0) Address: FFA0H After Reset: 00H Symbol ASIM0 TXE0...
Page 247 µPD780812, µPD780814, µPD78F0818 (b) Asynchronous serial interface status register (ASIS0) ASIS0 can be read using an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 17-7: Asynchronous serial interface status register (ASIS0) Address: FFA1H After Reset: 00H Symbol ASIS0 OVE0...
Page 248 µPD780812, µPD780814, µPD78F0818 (c) Baud rate generator control register (BRGC0) BRGC0 can be set by an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 17-8: Baud rate generator control register (BRGC0) Address: FFA2H After Reset: 00H Symbol BRGC0 TPS02...
Page 249 µPD780812, µPD780814, µPD78F0818 The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. • Use of main system clock to generate a transmit/receive clock for baud rate The main system clock is divided to generate the transmit/receive clock. The baud rate generated by the main system clock is determined according to the following formula.
Page 250 µPD780812, µPD780814, µPD78F0818 • Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per frame and the counter’s division rate [1/(16 + k)]. Table 17-4 describes the relation between the main system clock and the baud rate and Figure 17-9 shows an example of a baud rate error tolerance range.
Page 251 µPD780812, µPD780814, µPD78F0818 Figure 17-9: Error Tolerance (when k = 0), including Sampling Errors Ideal sampling point 256T 288T 320T 352T 304T 336T Basic timing START STOP (clock cycle T) 15.5T High-speed clock (clock cycle T’) START STOP enabling normal Sampling error reception 30.45T...
Page 252 µPD780812, µPD780814, µPD78F0818 (2) Communication operations (a) Data format As shown in Figure 17-10, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. The asynchronous serial interface mode register (ASIM0) is used to set the character bit length, parity selection, and stop bit length within each data frame.
Page 253 µPD780812, µPD780814, µPD78F0818 (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected.
Page 254 µPD780812, µPD780814, µPD78F0818 (c) Transmission The transmit operation is started when transmit data is written to the transmit shift register (TXS0). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXS0, thereby emptying TXS0, after which a transmit completion interrupt (INTST) is issued.
Page 255 µPD780812, µPD780814, µPD78F0818 (d) Reception The receive operation is enabled when “1” is set to bit 6 (RXE0) of the asynchronous serial interface mode register (ASIM0), and input data via RxD pin is sampled. The serial clock specified by ASIM0 is used when sampling the RxD pin. When the RxD pin goes low, the 5-bit counter begins counting and the start timing signal for data sampling is output if half of the specified baud rate time has elapsed.
Page 256 µPD780812, µPD780814, µPD78F0818 (e) Receive errors Three types of errors can occur during a receive operation: parity error, framing error, or overrun error. If, as the result of the data reception, an error flag is set to the asynchronous serial interface status register (ASIS0), a receive error interrupt (INTSER) will occur.
Page 257: Standby Function
µPD780812, µPD780814, µPD78F0818 17.6 Standby Function Serial transfer operations can be performed during HALT mode. During STOP mode, serial transfer operations are stopped and the values in the asynchronous serial interface mode register (ASIM0), transmit shift register (TXS0), receive shift register (RXS0), and receive buffer register (RXB0) remain as they were just before the clock was stopped.
Page 258 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 259: Chapter 18 Can Controller
µPD780812, µPD780814, µPD78F0818 Chapter 18 CAN Controller Table 18-1: Outline of the Function Feature Details CAN2.0 with active extended frame capability Protocol (Bosch specification 2.0 part B) Baudrate Max. 500Kb at 8 MHz clock supply Bus line control CMOS in / out for external transceiver Clock Selected by register CPU RAM area with shared access...
Page 260: Protocol
µPD780812, µPD780814, µPD78F0818 18.1 Protocol CAN is an abreviation of "Controller Area Network", and is a class C high speed multiplexed commu- nication protocol for real time communication in vehicle. CAN is being standardized in ISO (International Organization for Standardization) and SAE (Society of Automotive Engineers). For more detailed information please refer to Bosch, CAN specification 2.0 from September 1991.
Page 261: Data Frame/Remote Frame
µPD780812, µPD780814, µPD78F0818 18.1.3 Data frame/remote frame Figure 18-1: Data Frame Data frame (11 + 1) (29 + 3) 0 ... 64 Bus idle Interframe space End of frame ACK field CRC field Data field Control field Arbitration field Start of frame Figure 18-2: Remote Frame Remote frame Bus idle...
Page 262 µPD780812, µPD780814, µPD78F0818 Description of each field 1. Start of frame: The start of data frame and remote frame are indicated. Figure 18-3: Data Frame (Interframe space S tart of frame (Arbitration field) on bus idle) 1 bit • The start of frame is denoted by the falling edge of the bus signal. •...
Page 263 µPD780812, µPD780814, µPD78F0818 Table 18-3: RTR Setting Frame Type RTR Bit Data frame Remote frame Table 18-4: Mode Setting Protocol Mode IDE Bit Standard format mode Expanded format mode 3. Control field: Data byte number N in the data field is set (N: 0 to 8). Figure 18-6: Control Field (Arbitration field) (Control field)
Page 264 µPD780812, µPD780814, µPD78F0818 5. CRC field: 15 bits CRC sequence to check the transmission error. Figure 18-8: CRC Field (Data field and control field) (CRC field) (ACK field) CRC sequence CRC delimiter (15 bits) (1 bit) • 15 bits CRC generation polynomial is expressed by P(X) = X + 1.
Page 265 µPD780812, µPD780814, µPD78F0818 8. Interframe space: This frame is inserted between the data frame, remote frame, error frame, overload frame and the next frame to indicate partitions between each frame. (A) Error active: Consists of 3 bits intermission and bus idle. Figure 18-11: Interframe Space/Error Active (Each frame) (Each frame)
Page 266: Error Frame
µPD780812, µPD780814, µPD78F0818 18.1.4 Error frame • This frame is output from the node if an error is detected. • When other nodes output 'Dominant level' to flag the passive error, the dominant level continues for 6 consecutive bits. The passive error flag consists of 6 consecutive Recessive bits unless a dominant bit from other nodes overwrite it.
Page 267: Overload Frame
µPD780812, µPD780814, µPD78F0818 18.1.5 Overload frame • This frame is output from the first bit of the intermission when the reception node has not completed the receiving operation. • When the bit error is detected in the intermission, this frame is output following the next bit after the bit error detection.
Page 268: Function
µPD780812, µPD780814, µPD78F0818 18.2 Function 18.2.1 Bus priority decision (1) When 1 node starts transmission • During bus idle, the node having the output data can transmit. (2) When more than 2 nodes start transmission • The node with the lower identifier wins the arbitration. •...
Page 269: Error Control Function
µPD780812, µPD780814, µPD78F0818 18.2.6 Error control function (1) Error types Table 18-12: Error Types Description of Error Detection State Type Detection Method Detection Condition Transmission/ Field/Frame Reception Comparison of output Disagreement of both Transmission/ Bit that output data on the Bit error level and level on the levels...
Page 270 µPD780812, µPD780814, µPD78F0818 (4) Error state 1. Types of error state • Three types of error state. These are error active, error passive and bus off. • The transmission error counter and the reception error counter control the error state. •...
Page 271 µPD780812, µPD780814, µPD78F0818 2. Error counter • Error counter counts up when error has occured, and counts down when transmission and reception are operated normally. Timing of count up and count down is first bit of the error deliminiter. Table 18-15: Error Counter State Transmission Error Counter Reception Error Counter...
Page 272: Baud Rate Control Function
µPD780812, µPD780814, µPD78F0818 18.2.7 Baud rate control function 1. Nominal bit time (8 to 25 time quantum) • Definition of 1 data bit time is as follows. Figure 18-15: Nominal Bit Time (8 to 25 Time Quantum) Normal bit time Sync Prop Phase...
Page 273 µPD780812, µPD780814, µPD78F0818 2. Adjusting synchronization of the data bit • Transmission node transmits data synchronizing with the transmission node bit timing. • Reception node adjusts synchronization at the level changing on the bus caused on hardware or software synchronization. (A) Hardware synchronization Bit synchronization adjustment when reception node detects the start of frame in the bus idle state.
Page 274 µPD780812, µPD780814, µPD78F0818 (B) Bit synchronization When the level change on the bus is detected during reception, bit synchronization is performed. • 2 types of synchronization can be performed. Normal operation: Level falling edge Low speed operation: Level falling edge and rising edge •...
Page 275: State Shift Chart
µPD780812, µPD780814, µPD78F0818 18.2.8 State shift chart Figure 18-18: Transmission State Shift Chart Reception Start of frame Bit error Arbitration field RTR = 1 Bit error Control field Reception RTR = 0 Bit error Data field Bit error CRC field ACK error ACK field Bit error...
Page 276 µPD780812, µPD780814, µPD78F0818 Figure 18-19: Reception State Shift Chart Transmission Start of frame Transmission Stuff error Arbitration field RTR = 1 Stuff error Control field RTR = 0 Stuff error Data field CRC error, stuff error CRC field ACK error, bit error ACK field Bit error, form error End of frame...
Page 277 µPD780812, µPD780814, µPD78F0818 Figure 18-20: Error State Shift Chart (A) Transmisssion Error active ≥ 128 TEC ≤ Error passive ≥ 256 Bus off TEC = 0 TEC = Transmission error counter (B) Reception Error active ≥ 128 Error passive REC ≤ REC = Reception error counter...
Page 278: Outline Description
µPD780812, µPD780814, µPD78F0818 18.3 Outline Description Figure 18-21: Structural Block Diagram Memory Access Receive Messages Receive Arbitration Messages Receive Messages Receive Messages Cycle Steal DMA Control SFR Access Extended RAM Memory Access Engine Interface Management Transmit Buffers Transmit (includes global registers) Buffers High Speed Protocol...
Page 279: Can Module Configuration
µPD780812, µPD780814, µPD78F0818 18.5 CAN Module Configuration The CAN-module consists of the following hardware. Table 18-17: CAN Configuration Item Configuration Message definition In RAM areas 1 (CTxD) CAN input/output 1 (CRxD) CAN control register (CANC) Transmit control register (TCR) Received message register (RMES) Redefinition control register (REDEF) CAN error status register (CANES) Transmit Error Counter (TEC)
Page 280: Operation
µPD780812, µPD780814, µPD78F0818 18.6 Operation 18.6.1 Special function register for CAN-module Table 18-18: SFR Definitions Address Register Name Symbol Bit Manipulation Units After 1 Bit 8 Bit 16 Bit Reset FFB0H CAN control register CANC — FFB1H Transmit control register —...
Page 281: Message And Buffer Configuation
µPD780812, µPD780814, µPD78F0818 18.7 Message and Buffer Configuation Table 18-20: Message and Buffer Structure Note2 Address Register Name Symbol After Reset Note1 00xH Transmit buffer 0 Note1 01xH Transmit buffer 1 Note1 02xH Rec. message 0 / Mask 0 Note1 03xH Rec.
Page 282: Transmit Buffer Structure
µPD780812, µPD780814, µPD78F0818 18.8 Transmit Buffer Structure The DCAN has two independent transmit buffers. The two buffers have a 16 byte data structure for standard and extended frames with a possibility to send 8 message data bytes. The structure of the transmit buffer is similar to the structure of the receive buffers.
Page 283: Transmit Message
µPD780812, µPD780814, µPD78F0818 18.9 Transmit Message Table 18-21: Transmit Message Structure Note Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCON DLC3 DLC2 DLC1 DLC0 Unused IDTX0 ID standard part IDTX1 ID standard part IDTX2...
Page 284 µPD780812, µPD780814, µPD78F0818 Transmit Message Definition This register controls the message definition bits of the control field of the CAN protocol. TCON is set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets TCON to an undefined value. Figure 18-23: Transmit Message Definition Bits Symbol Address...
Page 285 µPD780812, µPD780814, µPD78F0818 Transmit Identifier Definition These registers set the message identifier in the arbitration field of the CAN protocol. IDTX0 to IDTX4 can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets IDTX0 to IDTX4 to an undefined value. Figure 18-24: Transmit Identifier Symbol Address...
Page 286 µPD780812, µPD780814, µPD78F0818 Transmit Data Definition These registers set the transmit message data of the data field in the CAN frame. DATA0 to DATA7 can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets DATA0 to DATA7 to an undefined value. Figure 18-25: Transmit Data Symbol Address...
Page 287: Transmit Structure
µPD780812, µPD780814, µPD78F0818 18.10 Transmit Structure The DCAN has up to 16 receive buffers. The number of used buffers is defined by the MCNT register. Unused receive buffers can be used as application RAM for the CPU. The receive data is stored direktly in this RAM area.
Page 288: Receive Message
µPD780812, µPD780814, µPD78F0818 18.11 Receive Message Table 18-22: Receive Message Structure Note Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IDCON DSTAT IDREC0 ID standard part IDREC1 ID standard part IDREC2 ID extended part IDREC3...
Page 289 µPD780812, µPD780814, µPD78F0818 Receive Control Bits Definition This register sets the receive control bits of the control field of the CAN protocol. IDCON can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets IDCON to an undefined value. Figure 18-26: Control Bits for Receive Identifier Symbol Address...
Page 290 µPD780812, µPD780814, µPD78F0818 Receive Status Bits Definition This register sets the receive status bits of the arbitration field of the CAN protocol. DSTAT can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets DSTAT to an undefined value. Figure 18-27: Receive Status Bits Symbol Address...
Page 291 µPD780812, µPD780814, µPD78F0818 Reserved Bit 1 Reserved bit 1 of received message was “0” Reserved bit 1 of received message was “1” Reserved Bit 0 Reserved bit 0 of received message was “0” Reserved bit 0 of received message was “1” Data Length Code Selection of DLC3 DLC2...
Page 292 µPD780812, µPD780814, µPD78F0818 Receive Identifier Definition These registers set the receive identifier definition of the control field of the CAN protocol. IDREC0 to IDREC4 can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets IDREC0 to IDREC4 to an undefined value. Figure 18-28: Receive Identifier Symbol Address...
Page 293 µPD780812, µPD780814, µPD78F0818 Receive Message Data Part These registers set the receive message data part of the CAN protocol. DATA0 to DATA7 can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets DATA0 to DATA7 to an undefined value. Figure 18-29: Receive Data Symbol Address...
Page 294: Mask Function
µPD780812, µPD780814, µPD78F0818 18.12 Mask Function Table 18-23: Mask Function Note1 Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCON Unused MREC0 ID standard part MREC1 ID standard part MREC2 ID extended part MREC3 ID extended part...
Page 295 µPD780812, µPD780814, µPD78F0818 Figure 18-30: Identifier Compare with Mask Received Identifier Compare Store on equal Bit by Bit Mask stored in Receive Buffer 0 or 2 Disable Compare for masked Bits Identifier stored in Receive Buffer This function implements the so-called basic-CAN behavior. The type of identifier is in this case fixed to standard or extended by the setup of the IDE bit in the receive buffer.
Page 296 µPD780812, µPD780814, µPD78F0818 Mask Identifier Control Bit Definition This register sets the mask identifier control bit of the CAN protocol. MCON can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets MCON to an undefined value. Figure 18-31: Control Bits for Mask Identifier Symbol Address...
Page 297 µPD780812, µPD780814, µPD78F0818 Mask Identifier Definition These register sets the mask identifier definition of the DCAN. MREC0 to MREC4 can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets MREC0 to MREC4 to an undefined value. Figure 18-32: Mask Identifier Symbol Address...
Page 298: Can
µPD780812, µPD780814, µPD78F0818 18.13 18.13.1 Status register CAN Control Register These register sets the CAN control definition of the CAN module. CANC can be set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets CANC to 01H. Figure 18-33: CAN Control Register ÷...
Page 299 µPD780812, µPD780814, µPD78F0818 SOFE Start of Frame Enable SOFOUT does not change SOFOUT toggles depending on the selected mode SOFSEL Start of Frame Output Function Select SOFOUT works as time stamp function SOFOUT signals SOF on the bus / Global time function Figure 18-34: DCAN Support Receive Int.
Page 300 µPD780812, µPD780814, µPD78F0818 Figure 18-35: Time Stamp Function Object n Object n Other valid or Valid message invalid message Valid message Enable SOF Edge for capture Edge for capture Figure 18-36: SOFOUT Toggle Function Any valid or Any valid or Any valid or invalid message invalid message...
Page 301: Can Error Status Register
µPD780812, µPD780814, µPD78F0818 18.13.2 CAN error status register These register sets the CAN error status of the transmission and reception. CANES has to be set with an 8-bit memory manipulation instruction. RESET input sets CANC to 00H. Figure 18-38: CAN Error Status Register Symbol Address After Reset R/W...
Page 302 µPD780812, µPD780814, µPD78F0818 WAKE Wakeup Condition Normal operation Sleep mode has been cancelled This bit is set and an error interrupt is generated under the following circumstances: a) A CAN bus activities occurs during SLEEP condition of CAN protocol. b) Any try to set sleep mode in CAN control register during receive or transmit operation will immediately set the Wake up condition.
Page 303 µPD780812, µPD780814, µPD78F0818 Caution: Don’t use bit operations on this SFR. The VALID, WAKE and OVER bits have a special behavior during CPU write operations. • Writing a zero “0” to them do not change them. • Writing a one “1” clears the associated bit. This avoids any timing conflicts between CPU access and internal activities.
Page 304 µPD780812, µPD780814, µPD78F0818 CAN Transmit Error Counter These register builds the transmit error counter of the data transmission. TEC can be read with an 8-bit memory manipulation instruction. RESET input sets TEC to 00H. Figure 18-39: Transmit Error Counter Symbol Address After Reset R/W TEC7...
Page 305 µPD780812, µPD780814, µPD78F0818 CAN Receive Error Counter These register builds the receive error counter of the data reception. REC can be read with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets REC to 00H. Figure 18-40: Receive Error Counter Symbol Address After Reset R/W...
Page 306 µPD780812, µPD780814, µPD78F0818 Message Count Register These register sets the number of receive message buffers and the RAM area of the receive message buffers which are handled by the DCAN-module. MCNT can be read with an 8-bit memory manipulation instruction. RESET input sets MCNT to C0H.
Page 307 µPD780812, µPD780814, µPD78F0818 The DCAN address definition gives the possibility to initialize the 78K0 with different memory configuration with the IXS register. In case of this product it is recommended to use the start address of the expansion RAM as given to the following table. Table 18-27: RAM Setting Setting of CADD Device...
Page 308: Baudrate Generation
µPD780812, µPD780814, µPD78F0818 18.14 Baudrate Generation Bitrate Prescaler These registers set the bitrate prescaler for the DCAN. BRPRS can be set with an 8-bit memory manipulation instruction. RESET input sets BRPRS to 00H. Figure 18-42: Bit Rate Prescaler Symbol Address After Reset R/W BRPRS PRM1...
Page 309 µPD780812, µPD780814, µPD78F0818 Synchronisation Control Registers 0 and 1 These registers define the bit timing of the DCAN. It selects the length of one data bit on the CAN bus and the position of the sample point during the bit timing. SYNC0 and SYNC1 can be read or written with an 8-bit memory manipulation instruction.
Page 310 µPD780812, µPD780814, µPD78F0818 Figure 18-43: Synchronization Control Register 0 and 1 (2/2) SPT4 SPT3 SPT2 SPT1 SPT0 Sample Point Position Other than under Setting prohibited (Output cycle of BRPRS) x 2 (Output cycle of BRPRS) x 3 (Output cycle of BRPRS) x 4 (Output cycle of BRPRS) x 5 (Output cycle of BRPRS) x 6 (Output cycle of BRPRS) x 7...
Page 311 µPD780812, µPD780814, µPD78F0818 Synchronization Control Register 1 This register defines the bit timing of the DCAN. It defines the synchronization jump width. This gives the possible range of resynchronization to different transmission speeds. SYNC1 can be read or written with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets SYNC1 to 0EH.
Page 312 µPD780812, µPD780814, µPD78F0818 RXONLY Receive Only Operation Normal operation Only receive operation, CAN does not activate transmit line This operation mode can be used for baudrate detection. It makes it possible to try different baudrate configurations without disturbing other CAN nodes on the bus. Differences to CAN protocol: •...
Page 313: Function Control
µPD780812, µPD780814, µPD78F0818 18.15 Function Control 18.15.1 Transmit control Transmit Control Register This register controls the transmission of the DCAN-module. The Transmit Control register provides complete control over the two transmit buffers and their status. It is possible to request and abort transmission of both buffers independently.
Page 314 µPD780812, µPD780814, µPD78F0818 An abort operation can cause different results dependent on the time it is set.. a) Abort is received before the start of the arbitration for transmit. The TXCn bit is reset showing that the buffer was not send to other nodes. b) Abort is received during the arbitration, but arbitration is lost.
Page 315: Receive Control
µPD780812, µPD780814, µPD78F0818 18.15.2 Receive control The receive message register mirrors the current status of the first 8 receive buffers. Each buffer has one status bit in this register. This bit is always set when a new message is completely stored in the associated buffer.
Page 316: Mask Control
µPD780812, µPD780814, µPD78F0818 18.15.3 Mask control The mask Control Register defines whether the DCAN compares the identifier of a received message in its whole length or some bits are not used for comparison. This functionality is provided by the use of mask information. The mask information defines for each bit of the identifier whether it is used for comparison or not.
Page 317 µPD780812, µPD780814, µPD78F0818 The following table shows which compare takes place for the different receive buffers. The ID in this table always represents the ID stored in the mentioned receive buffer. The table also shows which buffers are used as mask information and do not receive messages. A global mask can be used for standard and extended frames at the same time.
Page 318: Special Functions
µPD780812, µPD780814, µPD78F0818 18.15.4 Special functions Redefinition Control Register These register controls redefinition of an identifier of a receive messages of the DCAN-module. REDEF can be written with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets REDEF to 00H. Figure 18-48: Redefinition Control Register ù...
Page 319 µPD780812, µPD780814, µPD78F0818 Setting the redefinition bit removes the selected receive buffer from the list of possible ID hits during identifier comparisions. There is one special case: The message is complete and the DCAN started the storage into the RAM. In this case the complete message is stored and the redefinition request is ignored.
Page 320: Interrupt Information
µPD780812, µPD780814, µPD78F0818 18.16 Interrupt Information 18.16.1 Interrupt vectors The DCAN peripheral supports four interrupt sources as shown in the following table. Table 18-29: Interrupt Sources Function Source Interrupt Flag Error counter Error Overrun error CEIF Wake up Receive Received frame is valid CRIF Transmit buffer 0 TXRQ0 is cleared...
Page 321: Standby Function
µPD780812, µPD780814, µPD78F0818 18.17 Standby Function 18.17.1 CPU halt mode The Halt mode is possible in conjunction with CAN sleep mode. 18.17.2 CPU stop mode The DCAN stops any activity when its clock supply stops. This may cause an errorneous behavior on the CAN bus when the clock is not sychronized to bus activities.
Page 322: Functional Description By Flowcharts
µPD780812, µPD780814, µPD78F0818 18.18 Functional Description by Flowcharts 18.18.1 Initialization Figure 18-49: Initialization Flow Chart RESET Software Init set INIT=1 in CANC BRPRS SYNC0/1 Initilialize message and mask data MCNT MASKC Write for BRPRS Clear INIT=0 in CANC SYNC0/1 MCNT MASKC is now disabled End Initialization...
Page 323: Prepare Transmit
µPD780812, µPD780814, µPD78F0818 18.18.2 Prepare transmit Figure 18-50: Transmit Preparation Transmit Wait or TXRQn Abort or Try other Buffer Write data Select Priority TXRQn = 1 End Transmit...
Page 324: Abort Transmit
µPD780812, µPD780814, µPD78F0818 18.18.3 Abort transmit Figure 18-51: Transmit Abort, Software Flow Transmission Abort TXAn TXRQn TXCn Transmit Transmit was successful was aborted before ABORT End Transmission Abort...
Page 325: Handling By The Dcan
µPD780812, µPD780814, µPD78F0818 18.18.4 Handling by the DCAN Figure 18-52: Handling of Semaphore Bits by DCAN-Module Data Storage Warns that data will be changed Write DN = 1 MUC = 1 Only for buffers that are declared for mask operation Write Identifier bytes...
Page 326: Receive Event Oriented
µPD780812, µPD780814, µPD78F0818 18.18.5 Receive event oriented Figure 18-53: Receive with Interrupt, Software Flow Receive Interrupt scans RMES or DN bits to find message Uses CLR1 Command Clear DN bit read or process data Data was changed DN = 0 by CAN during the processing MUC = 0...
Page 327: Receive Task Oriented
µPD780812, µPD780814, µPD78F0818 18.18.6 Receive task oriented Figure 18-54: Receive, Software Polling Receive Polled Uses CLR1 command Clear DN bit Read or process data Data was changed by CAN during the DN = 0 processing MUC = 0 End Receive Polled...
Page 328 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 329: Chapter 19 Interrupt Functions
µPD780812, µPD780814, µPD78F0818 Chapter 19 Interrupt Functions 19.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in a disabled state. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal.
Page 330: Interrupt Sources And Configuration
µPD780812, µPD780814, µPD78F0818 19.2 Interrupt Sources and Configuration There are total of 24 non-maskable, maskable, and software interrupts in the interrupt sources. Table 19-1: Interrupt Source List Note 1 Note 2 Interrupt Source Maskability Interrupt Internal/ Vector Basic Priority Name Trigger External Address...
Page 331 µPD780812, µPD780814, µPD78F0818 Figure 19-1: Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal Bus Vector Table Priority Control Interrupt Address Circuit Request Generator Standby Release Signal (B) Internal maskable interrupt Internal Bus Vector Table Priority Control Address Interrupt Circuit Generator...
Page 332 µPD780812, µPD780814, µPD78F0818 Figure 19-1: Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt Internal Bus External Interrupt Mode Register (EGN, EGP) Vector Table Priority Control Address Interrupt Edge Circuit Generator Request Detector Standby Release Signal (D) External maskable interrupt (INTKR) Internal Bus Vector Table Priority Control...
Page 333: Interrupt Function Control Registers
µPD780812, µPD780814, µPD78F0818 19.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L, PR0H, PR1L) •...
Page 334 µPD780812, µPD780814, µPD78F0818 (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
Page 335 µPD780812, µPD780814, µPD78F0818 (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, MK1L and MK1H are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.
Page 336 µPD780812, µPD780814, µPD78F0818 (3) Priority specify flag registers (PR0L, PR0H, PR1L, PR1H) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, PR1L and PR1H are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.
Page 337 µPD780812, µPD780814, µPD78F0818 (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) EGP and EGN specify the valid edge to be detected on pins P00 to P03. EGP and EGN can be read or written to with a 1-bit or 8-bit memory manipulation instruction. These registers are set to 00H when the RESET signal is output.
Page 338 µPD780812, µPD780814, µPD78F0818 (5) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt servicing are mapped.
Page 339: Interrupt Servicing Operations
µPD780812, µPD780814, µPD78F0818 19.4 Interrupt Servicing Operations 19.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts.
Page 340 µPD780812, µPD780814, µPD78F0818 Figure 19-7: Flowchart from Non-Maskable Interrupt Generation to Acknowledge Start WDTM4 = 1 (with watchdog timer mode selected)? Interval timer Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt selected)? Reset processing Interrupt request generation WDT interrupt servicing? Interrupt request held pending Interrupt control...
Page 341 µPD780812, µPD780814, µPD78F0818 Figure 19-9: Non-Maskable Interrupt Request Acknowledge Operation If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request 1 Instruction NMI Request NMI Request Reserve Execution Reserved NMI Request Processing (b) If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution Main Routine...
Page 342: Maskable Interrupt Request Acknowledge Operation
µPD780812, µPD780814, µPD78F0818 19.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1).
Page 343 µPD780812, µPD780814, µPD78F0818 Figure 19-10: Interrupt Request Acknowledge Processing Algorithm Start xxIF = 1? Yes (Interrupt Request Generation) xxMK = 0? Interrupt request reserve Yes (High priority) xxPR = 0? No (Low Priority) Any high- priority interrupt among simultaneously generated simultaneously xxPR = 0 interrupts? generated xxPR = 0...
Page 344: Software Interrupt Request Acknowledge Operation
µPD780812, µPD780814, µPD78F0818 Figure 19-11: Interrupt Request Acknowledge Timing (Minimum Time) 6 Clocks PSW and PC Save, Interrupt CPU Processing Instruction Instruction Jump to Interrupt Servicing Servicing Program xxIF (xxPR = 1) 8 Clocks xxIF (xxPR = 0) 7 Clocks Remark: 1 clock: : CPU clock)
Page 345: Multiple Interrupt Servicing
µPD780812, µPD780814, µPD78F0818 19.4.4 Multiple interrupt servicing A multiple interrupt consists in acknowledging another interrupt during the execution of the interrupt. A multiple interrupt is generated only in the interrupt request acknowledge enable state (IE = 1) (except non-maskable interrupt). As soon as an interrupt request is acknowledged, it enters the acknowledge disable state (IE = 0).
Page 346 µPD780812, µPD780814, µPD78F0818 Figure 19-13: Multiple Interrupt Example (1/2) Example 1. Two multiple interrupts generated Main Processing INTxx INTyy INTzz Servicing Servicing Servicing IE = 0 IE = 0 IE = 0 INTyy INTzz (PR = 0) (PR = 0) INTxx (PR = 1) RETI...
Page 347 µPD780812, µPD780814, µPD78F0818 Figure 19-13: Multiple Interrupt Example (2/2) Example 3. A multiple interrupt is not generated because interrupts are not enabled Main Processing INTxx INTyy Servicing Servicing IE = 0 INTyy INTxx (PR = 0) (PR = 0) RETI IE = 0 1 Instruction Execution...
Page 348: Interrupt Request Reserve
µPD780812, µPD780814, µPD78F0818 19.4.5 Interrupt request reserve Some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interupt request is generated during the execution. The following shows such instructions (interrupt request reserve instruction). •...
Page 349 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 350: Chapter 20 Key Return Mode
µPD780812, µPD780814, µPD78F0818 Chapter 20 Key Return Mode 20.1 Key Return Mode Functions The Key Return Mode allows it to build up a keyboard by using a detection of a low level at any bit of port 4. When the Key Return Mode is enabled, a low level at any bit of port 4 generates a Key Return Interrupt.
Page 351: Key Return Mode Control Registers
µPD780812, µPD780814, µPD78F0818 20.3 Key Return Mode Control Registers The following two types of registers are used to control the key return mode: • Key Return Mode Register (KRM) • Port Mode Register (PM4) (1) Key Return Mode Register (KRM) The register enables the key return mode.
Page 352 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 353: Chapter 21 Standby Function
µPD780812, µPD780814, µPD78F0818 Chapter 21 Standby Function 21.1 Standby Function and Configuration 21.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock.
Page 354: Standby Function Control Register
µPD780812, µPD780814, µPD78F0818 21.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 355: Standby Function Operations
µPD780812, µPD780814, µPD78F0818 21.2 Standby Function Operations 21.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. Table 21-1: HALT Mode Operating Status HALT mode setting HALT execution during main...
Page 356 µPD780812, µPD780814, µPD78F0818 (2) HALT mode clear The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode. If interrupt acknowledge is enabled, vectored interrupt service is carried out.
Page 357 µPD780812, µPD780814, µPD78F0818 (d) Clear upon RESET input As is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 21-3: HALT Mode Release by RESET Input Wait HALT : 16.3 ms) Instruction RESET Signal...
Page 358: Stop Mode
µPD780812, µPD780814, µPD78F0818 21.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions: 1. When the STOP mode is set, the X2 pin is internally connected to V via a pull- up resistor to minimize leakage current at the crystal oscillator.
Page 359 µPD780812, µPD780814, µPD78F0818 (2) STOP mode release The STOP mode can be cleared with the following three types of sources. (a) Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
Page 360 µPD780812, µPD780814, µPD78F0818 (c) Release by RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 21-5: Release by STOP Mode RESET Input Wait STOP : 16.3 ms) Instruction RESET Signal Oscillation...
Page 361 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 362: Chapter 22 Reset Function
µPD780812, µPD780814, µPD78F0818 Chapter 22 Reset Function 22.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detection (3) Internal reset by main clock failure detection. External reset and internal reset have no functional differences.
Page 363 µPD780812, µPD780814, µPD78F0818 Figure 22-2: Timing of Reset Input by RESET Input Oscillation Reset Period Normal Operation Normal Operation Stabilization (Oscillation Stop) (Reset Processing) Time Wait RESET Internal Reset Signal Delay Delay High Impedance Port Pin Figure 22-3: Timing of Reset due to Watchdog Timer Overflow Reset Period Oscillation Normal Operation...
Page 364 µPD780812, µPD780814, µPD78F0818 Table 22-1: Hardware Status after Reset (1/3) Hardware Status after Reset Note 1 Program counter (PC) The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2...
Page 365 µPD780812, µPD780814, µPD78F0818 Table 22-1: Hardware Status after Reset (2/3) Hardware Status after Reset 8-bit timer/event counters Timer register (TM50, TM51) 50 and 51 Compare register (CR50, CR51) Clock select register (TCL50, TCL51) Mode control register (TMC50, TMC51) Watch timer Mode register (WTM) Clock selection register (WDCS) Watchdog timer...
Page 366 µPD780812, µPD780814, µPD78F0818 Table 22-1: Hardware Status after Reset (3/3) Hardware Status after Reset Control register (CANC) Transmit control register (TCR) Receive message register (RMES) Redefinition register (REDEF) Error status register (CANES) Transmit error counter register (TEC) Receive error counter register (REC) Message count register (MCNT) Bit rate prescaler register (BRPRS) Synchronous control register (SYNC0)
Page 367 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 368: Chapter 23 Μpd78F0818
µPD780812, µPD780814, µPD78F0818 Chapter 23 µPD78F0818 The flash memory versions of the µPD780814 Subseries includes the µPD78F0818 The µPD78F0818 replaces the internal mask ROM of the µPD780814 with flash memory to which a program can be written, deleted and overwritten while mounted on the substrate. Table 23-1 lists the differences among the µPD78F0818 and the mask ROM versions.
Page 369: Memory Size Switching Register (Ims)
µPD780812, µPD780814, µPD78F0818 23.1 Memory Size Switching Register (IMS) This register specifies the internal memory size by using the memory size switching register (IMS), so that the same memory map as on the mask ROM version can be achieved. IMS is set with an 8-bit memory manipulation instruction. RESET input sets this register to the value indicated in Table 23-2.
Page 370: Internal Extension Ram Size Switching Register
µPD780812, µPD780814, µPD78F0818 23.2 Internal Extension RAM Size Switching Register The µPD78F0818 allows users to define its internal extension RAM size by using the internal extension RAM size switching register (IXS), so that the same memory mapping as that of a mask ROM version with a different internal extension RAM is possible.
Page 371: Flash Memory Programming
µPD780812, µPD780814, µPD78F0818 23.3 Flash memory programming On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is done after connecting a dedicated flash writer (Flashpro) to the host machine and target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro.
Page 372: Flash Memory Programming Function
µPD780812, µPD780814, µPD78F0818 23.3.3 Flash memory programming function Flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. The main functions are listed in Table 23-5. Table 23-5: Main Functions of Flash Memory Programming Function Description Reset...
Page 373: Flash Programming Precautions
µPD780812, µPD780814, µPD78F0818 Figure 23-5: Flashpro Connection Using UART Method Flashpro µPD78F0818 RESET RESET Figure 23-6: Flashpro Connection Using Pseudo 3-wire Serial I/O Flashpro µPD78F0818 RESET RESET (Serial clock input) (Serial data input) (Serial data output) 10.3 V applied from the o-board programming tool. RESET: A RESET is generated and the device is set to the on-board programming mode.
Page 374 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 375: Chapter 24 Instruction Set
µPD780812, µPD780814, µPD78F0818 Chapter 24 Instruction Set This chapter describes each instruction set of the µ PD780948 subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 series USER’S MANUAL - Instruction (U12326E).”...
Page 376: Legends Used In Operation List
µPD780812, µPD780814, µPD78F0818 24.1 Legends Used in Operation List 24.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them.
Page 377: Description Of "Operation" Column
µPD780812, µPD780814, µPD78F0818 24.1.2 Description of “operation” column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair...
Page 378: Operation List
µPD780812, µPD780814, µPD78F0818 24.2 Operation List Clock Flag Instruc- Mnemonic Operands Byte Operation tion Group Z AC CY Note 1 Note 2 r ← byte r, #byte – (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte – A ← r Note 3 A, r –...
Page 379 µPD780812, µPD780814, µPD78F0818 Clock Flag Instruc- Mnemonic Operands Byte Operation tion Group Z AC CY Note 1 Note 2 rp ← word rp, #word – (saddrp) ← word saddrp, #word sfrp ← word sfrp, #word – AX ← (saddrp) AX, saddrp (saddrp) ←...
Page 380 µPD780812, µPD780814, µPD78F0818 Clock Flag Instruc- Mnemonic Operands Byte Operation tion Group Z AC CY Note 1 Note 2 A, CY ← A – byte A, #byte – (saddr), CY ← (saddr) – byte saddr, #byte A, CY ← A – r Note 3 A, r –...
Page 381 µPD780812, µPD780814, µPD78F0818 Clock Flag Instruc- Mnemonic Operands Byte Operation tion Group Z AC CY Note 1 Note 2 A ← A byte A, #byte – (saddr) ← (saddr) byte saddr, #byte A ← A r Note 3 A, r –...
Page 382 µPD780812, µPD780814, µPD78F0818 Clock Flag Instruc- Mnemonic Operands Byte Operation tion Group Z AC CY Note 1 Note 2 AX, CY ← AX + word ADDW AX, #word – 16-bit AX, CY ← AX – word SUBW AX, #word – operation CMPW AX, #word...
Page 383 µPD780812, µPD780814, µPD78F0818 Clock Flag Instruc- Mnemonic Operands Byte Operation tion Group Z AC CY Note 1 Note 2 CY ← CY (saddr.bit) CY, saddr.bit CY ← CY sfr.bit CY, sfr.bit – CY ← CY A.bit AND1 CY, A.bit – CY ←...
Page 384 µPD780812, µPD780814, µPD78F0818 Clock Flag Instruc- Mnemonic Operands Byte Operation tion Group Z AC CY Note 1 Note 2 (SP – 1) ← (PC + 3) , (SP – 2) ← (PC + 3) CALL !addr16 – PC ← addr16, SP ← SP – 2 (SP –...
Page 385 µPD780812, µPD780814, µPD78F0818 Clock Flag Instruc- Mnemonic Operands Byte Operation tion Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 saddr.bit, $addr16 PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 –...
Page 386: Instructions Listed By Addressing Type
µPD780812, µPD780814, µPD78F0818 24.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ...
Page 387 µPD780812, µPD780814, µPD78F0818 Second Operand [HL + byte] Note #byte saddr !addr16 PSW [DE] [HL] $addr16 None [HL + B] First Operand [HL + C] ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC SUBC SUBC SUBC SUBC ADDC SUBC B, C DBNZ...
Page 388 µPD780812, µPD780814, µPD78F0818 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand Note #word sfrp saddrp !addr16 None 1st Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW MOVW...
Page 389 µPD780812, µPD780814, µPD78F0818 (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP...
Page 390 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 391: Appendix A Development Tools
µPD780812, µPD780814, µPD78F0818 Appendix A Development Tools The following development tools are available for the development of systems that employ the µPD780814 Subseries. Figure A-1 shows the development tool configuration. Figure A-1: Development Tool Configuration Embedded Software Language Processing Software •...
Page 392: Language Processing Software
µPD780812, µPD780814, µPD78F0818 A.1 Language Processing Software This assembler converts programs written in mnemonics into an object code RA78K/0 executable with a microcomputer. Assembler Package Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler is used in combination with an optional device file (DF780945).
Page 393: Flash Memory Writing Tools
µPD780812, µPD780814, µPD78F0818 A.2 Flash Memory Writing Tools Dedicated flash writer for microcontrollers with on-chip flash memory. Flashpro Flash Writer Flashpro is a product of Naitoudensei Machida Seisakusho, Co., Ltd. µ PD780814 Subseries flash memory writing adapter used connected to Flashpro. Flash memory writing adapter FA-64GK-SL These are products of Naitoudensei Machida Seisakusho, Co., Ltd.
Page 394: Software
µPD780812, µPD780814, µPD78F0818 A.3.2 Software (1/2) SM78K0 This system simulator is used to perform debugging at C source level or assembler System Simulator level while simulating the operatin of the target system on a host machine. The SM78K0 operates on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency...
Page 395 µPD780812, µPD780814, µPD78F0818 A.3.2 Software (2/2) ID78K0 This is a control program used to debug the 78K/0 Series. Integrated Debugger The graphical user interfaces employed are Windows for personal computers and OSF/Motif for EWSs, offering the standard appearance and operability typical of these interfaces.
Page 396: Os For Ibm Pc
µPD780812, µPD780814, µPD78F0818 A.4 OS for IBM PC The following OSs for IBM PCs are supported. To operate SM78K0, ID78K0, and FE9200 (see B.2 Fuzzy Inference Development Support System), Windows (Ver. 3.0 to Ver. 3.1) is necessary. Version PC DOS Ver.
Page 397: Development Environment When Using Ie-78001-R-A
µPD780812, µPD780814, µPD78F0818 A.5 Development Environment when Using IE-78001-R-A When using the IE-78001-R-A as the in-circuit emulator, the following debugging tools are required. This in-circuit emulator is used to debug hardware and software when an applica- IE-78001-R-A In-Circuit Emulator tion system using the 78K/0 Series is developed. It supports the integrated debugger (ID78K0).
Page 398 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 399: Appendix B Embedded Software
µPD780812, µPD780814, µPD78F0818 Appendix B Embedded Software For efficient development and maintenance of the µPD780814 Subseries, the following embedded software products are available.
Page 400: Real-Time Os (2/2)
µPD780812, µPD780814, µPD78F0818 B.1 Real-Time OS (1/2) µ RX78K/0 RX78K/0 is a real-time OS conforming with the ITRON specifications. Real-time OS Tool (configurator) for generating nucleus of RX78K/0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78K/0) and device file. µ...
Page 401 µPD780812, µPD780814, µPD78F0818 B.1 Real-Time OS (2/2) µ MX78K0 lTRON specification subset OS. Nucleus of MX78K0 is supplied. This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next.
Page 402: Fuzzy Inference Development Support System
µPD780812, µPD780814, µPD78F0818 Fuzzy Inference Development Support System FE9000/FE9200 Program that supports input, edit, and evaluation (simulation) of fuzzy knowledge Fuzzy knowledge data creation tool data (fuzzy rule and membership function). FE9200 works on Windows. µ Part number: SxxxxFE9000 (PC-9800 Series) µ...
Page 403 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 404: Appendix C Register Index
µPD780812, µPD780814, µPD78F0818 Appendix C Register Index C.1 Register Index (In Alphabetical Order with Respect to Register Names) A/D conversion result register (ADCR1) … 205 A/D converter mode register (ADM1) … 207 Analog input channel specification register (ADS1) … 208 Asynchronous serial interface mode register (ASIM0) …...
Page 405 µPD780812, µPD780814, µPD78F0818 Key return mode register (KRM) … 94, 349, 350 Memory size switching register (IMS) … 368 Oscillation stabilization time selection register (OSTS) … 353 Port 0 (P0) … 83 Port 1 (P1) … 84 Port 2 (P2) … 85 Port 4 (P4) …...
Page 406 µPD780812, µPD780814, µPD78F0818 Serial I/O shift register 20 (SIO20) … 223, 224 Serial I/F receive data buffer register (SIRB20) … 223, Serial I/F operation mode register 20 (CSIM20) … 223, 224, 225, 228, 229 16-bit timer mode control register (TMC0) … 118, 119 16-bit timer mode control register (TMC2) …...
Page 407: Register Index (In Alphabetical Order With Respect To Register Symbol)
µPD780812, µPD780814, µPD78F0818 C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR1 : A/D conversion result register 1 ADM1 : A/D converter mode register ADS1 : Analog input channel specification register ASIM0 : Asynchronous serial interface mode register ASIS0 : Asynchronous serial interface status register BRGC0 : Baud rate generator control register...
Page 408 µPD780812, µPD780814, µPD78F0818 : Port mode register 0 : Port mode register 2 : Port mode register 4 : Port mode register 5 : Port mode register 6 : Port mode register 7 PRM0 : Prescaler mode register 0 PRM2 : Prescaler mode register 2 PR0H : Priority specify flag register 0H...
Page 409 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 410: Appendix D Revision History
µPD780812, µPD780814, µPD78F0818 Appendix D Revision History The following shows the revision history up to present. Application portions signifies the chapter of each edition. Edition No. Main revised contens from old edition Revised Sections...
Page 411 µPD780812, µPD780814, µPD78F0818 Appendix D Revision History Edition No. Main revised contens from old edition Revised Sections...
Page 412 µPD780812, µPD780814, µPD78F0818 [Memo]...
Page 413 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation.

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