Page 1 User’s Manual µ µ µ µ PD789046 Subseries 8-Bit Single-Chip Microcontrollers µ µ µ µ PD789046 µ µ µ µ PD78F9046 Document No. U13600EJ2V0UMJ1 (2nd edition) Date Published October 2000 N CP(K) © 1998, 1999 Printed in Japan...
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Page 3: Table Of Contents
SUMMARY OF CONTENTS CHAPTER 1 GENERAL ............................23 CHAPTER 2 PIN FUNCTIONS..........................29 CHAPTER 3 CPU ARCHITECTURE.........................37 CHAPTER 4 PORT FUNCTIONS........................59 CHAPTER 5 CLOCK GENERATION CIRCUIT ....................75 CHAPTER 6 16-BIT TIMER ..........................85 CHAPTER 7 8-BIT TIMER/EVENT COUNTER....................101 CHAPTER 8 WATCH TIMER ..........................113 CHAPTER 9 WATCHDOG TIMER ........................119 CHAPTER 10 SERIAL INTERFACE 20......................125...
Page 4: Notes For Cmos Devices
Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 5 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 6: Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 7 Major Revision in This Edition Page Description Completion of development of µ PD789046 and µ PD78F9046 Throughout p.34 Change of recommended connection of unused pins in Table 2-1 p.86 Correction of Figure 6-1 Addition of cautions on rewriting CR90 to Section 6.4.1 p.92 p.98 Addition of cautions on 16-bit timer to Section 6.5...
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Page 9 INTRODUCTION Readers This manual is intended for user engineers who understand the functions of the µ PD789046 Subseries to design and develop its application systems and programs. Target products: • µ PD789046 Subseries: µ PD789046 and µ PD78F9046 Purpose This manual is intended for users to understand the functions described in the Organization below.
Page 10 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. English Japanese µ PD789046 Data Sheet U13380E U13380J µ PD78F9046 Preliminary Product Information U13546E U13546J µ...
Page 11 Japanese SEMICONDUCTORS SELECTION GUIDE Products & Package X13769X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Device C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
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Page 13 TABLE OF CONTENTS CHAPTER 1 GENERAL..........................23 Features ............................23 Applications..........................23 Ordering Information .........................23 Pin Configuration (Top View)....................24 78K/0S Series Development ......................25 Block Diagram ..........................27 Functions ............................28 CHAPTER 2 PIN FUNCTIONS ........................29 Pin Function List ........................29 Description of Pin Functions ....................31 2.2.1 P00 to P07 (Port 0)........................31 2.2.2 P10 to P17 (Port 1)........................31...
Page 14 3.3.3 Table indirect addressing ......................51 3.3.4 Register addressing ........................51 Operand Address Addressing ....................52 3.4.1 Direct addressing ........................52 3.4.2 Short direct addressing .......................53 3.4.3 Special function register (SFR) addressing.................54 3.4.4 Register addressing ........................55 3.4.5 Register indirect addressing......................56 3.4.6 Based addressing........................57 3.4.7 Stack addressing.........................57 CHAPTER 4 PORT FUNCTIONS ......................
Page 15 6.4.1 Operation as timer interrupt......................92 6.4.2 Operation as timer output ......................94 6.4.3 Capture operation........................95 6.4.4 16-bit timer counter 90 readout ....................96 6.4.5 Buzzer output operation ......................97 Notes on 16-Bit Timer ........................98 CHAPTER 7 8-BIT TIMER/EVENT COUNTER ..................101 Functions of 8-Bit Timer/Event Counter ................101 8-Bit Timer/Event Counter Configuration ................102 8-Bit Timer/Event Counter Control Registers................103 Operation of 8-Bit Timer/Event Counter ................105...
Page 16 11.1 Interrupt Function Types......................159 11.2 Interrupt Sources and Configuration ..................159 11.3 Interrupt Function Control Registers..................162 11.4 Interrupt Processing Operation ....................168 11.4.1 Non-maskable interrupt request acceptance operation.............168 11.4.2 Maskable interrupt request acceptance operation ..............170 11.4.3 Multiplexed interrupt processing....................172 11.4.4 Interrupt request reserve ......................174 CHAPTER 12 STANDBY FUNCTION .....................
Page 17 APPENDIX B EMBEDDED SOFTWARE....................211 APPENDIX C REGISTER INDEX ......................213 Register Name Index (Alphabetic Order) ................213 Register Symbol Index (Alphabetic Order)................215 APPENDIX D REVISION HISTORY......................217 User's Manual U13600EJ2V0UM00...
Page 18 LIST OF FIGURES (1/3) Figure No. Title Page Pin Input/Output Circuits ..........................35 Memory Map ( µ PD789046)........................37 Memory Map ( µ PD78F9046)........................38 Data Memory Addressing Modes ( µ PD789046) ..................40 Data Memory Addressing Modes ( µ PD78F9046) ..................41 Program Counter Configuration .........................42 Program Status Word Configuration ......................42 Stack Pointer Configuration ........................44 Data to be Saved to Stack Memory ......................44...
Page 19 LIST OF FIGURES (2/3) Figure No. Title Page Settings of 16-Bit Timer Mode Control Register 90 for Timer Output Operation........94 Timer Output Timing ..........................94 Settings of 16-Bit Timer Mode Control Register 90 for Capture Operation ..........95 6-10 Capture Operation Timing (Both Edges of CPT90 Pin Are Specified) ............
Page 20 LIST OF FIGURES (3/3) Figure No. Title Page 11-6 Format of Key Return Mode Register 00 ....................167 11-7 Block Diagram of Falling Edge Detection Circuit ..................167 11-8 Flowchart from Non-Maskable Interrupt Request Generation to Acceptance..........169 11-9 Timing of Non-Maskable Interrupt Request Acceptance................169 11-10 Accepting Non-Maskable Interrupt Request ....................169 11-11...
Page 21 LIST OF TABLES (1/2) Table No. Title Page Type of Input/Output Circuit for Each Pin and Handling of Unused Pins ..........34 Internal ROM Capacity ..........................39 Vector Table.............................. 39 Special Function Registers ........................47 Port Functions ............................60 Configuration of Port ..........................61 Port Mode Register and Output Latch Settings for Using Alternate Functions .........
Page 22: List Of Tables
LIST OF TABLES (2/2) Table No. Title Page 10-6 Relationships between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) ........................142 10-7 Receive Error Causes ..........................147 11-1 Interrupt Sources .............................160 11-2 Interrupt Request Signals and Corresponding Flags ................162 11-3 Time from Generation of Maskable Interrupt Request to Processing ............170 12-1...
Page 23: Chapter 1 General
CHAPTER 1 GENERAL 1.1 Features • ROM and RAM capacity Item Program Memory Data Memory Product Name (Internal High-Speed RAM) µ PD789046 Masked ROM 16 Kbytes 512 bytes µ PD78F9046 Flash memory 16 Kbytes • Minimum instruction execution time changeable from high-speed (0.4 µ s: Main system clock 5.0-MHz operation) to ultra-low speed (122 µ...
Page 24: Pin Configuration (Top View)
CHAPTER 1 GENERAL 1.4 Pin Configuration (Top View) 44-pin plastic LQFP (10 × × × × 10 mm) • µ PD789046GB-×××-8ES µ PD78F9046GB-8ES 44 43 42 41 40 39 38 37 36 35 34 P47/KR07 P46/KR06 P20/SCK20/ASCK20 P45/KR05 P21/SO20/TxD20 P44/KR04 P22/SI20/RxD20 P23/SS20 P43/KR03...
Page 25: 0S Series Development
CHAPTER 1 GENERAL 1.5 78K/0S Series Development The 78K/0S Series products are shown below. Subseries names are indicated in frames. In production Under development For small-scale, general- purpose applicationns µ µ Device developed by adding the subsystem clock to the PD789026 44-pin PD789046 µ...
Page 26 CHAPTER 1 GENERAL The following table lists the major differences in functions between the subseries. Function ROM Size Timer 8-Bit 10-Bit Serial Interface Minimum Remarks Value Subseries 8-Bit 16-Bit Watch WDT µ PD789046 − − − Small-scale, 16 K 1 ch 1 ch 1 ch 1 ch...
Page 27: Block Diagram
CHAPTER 1 GENERAL 1.6 Block Diagram P00 to P07 TI80/TO80/P27 PORT 0 8-bit TIMER80 CPT90/INTP2/P26 PORT 1 P10 to P17 TO90/P30 16-bit TIMER90 BZO90/P31 P20 to P27 PORT 2 WATCH TIMER 78K/0S PORT 3 P30, P31 WATCHDOG TIMER CPU CORE SCK20/ASCK20/P20 PORT 4 P40 to P47...
Page 28: Functions
CHAPTER 1 GENERAL 1.7 Functions µ PD789046 µ PD78F9046 Product Item Internal memory ROM structure Masked ROM Flash memory ROM capacity 16 Kbytes High-speed RAM 512 bytes • 0.4/1.6 µ s (operation with main system clock running at 5.0 MHz) Minimum instruction execution time •...
Page 29: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List Port pins Pin Name Function After Reset Alternate Function − P00 to P07 Port 0 Input 8-bit input/output port Can be set to either input or output in 1-bit units When used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (PU0).
Page 30 CHAPTER 2 PIN FUNCTIONS Non-port pins Pin Name Function After Reset Alternate Function INTP0 Input Input External interrupt input for which effective edges (rising and/or falling edges) can be set INTP1 INTP2 P26/CPT90 KR00 to KR07 Input Detection of key return signal Input P40 to P47 SI20...
Page 31: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (PU0).
Page 32: P30, P31 (Port 3)
CHAPTER 2 PIN FUNCTIONS (g) ASCK20 This is the serial clock input pin of the asynchronous serial interface. (h) CPT90 This is the capture edge input pin of the 16-bit timer counter. (i) INTP0 to INTP2 These are external interrupt input pins for which the valid edge (rising edge, falling edge, and both the rising and falling edges) can be specified.
Page 33: Reset
CHAPTER 2 PIN FUNCTIONS 2.2.6 RESET An active-low system reset signal is input to this pin. 2.2.7 X1, X2 These pins are used to connect a crystal resonator for main system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 2.2.8 XT1, XT2 These pins are used to connect a crystal resonator for subsystem clock oscillation.
Page 34: Pin Input/Output Circuits And Handling Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin Input/Output Circuits and Handling of Unused Pins Table 2-1 lists the types of input/output circuits for each pin and explains how unused pins are handled. Figure 2-1 shows the configuration of each type of input/output circuit. Table 2-1.
Page 35 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin Input/Output Circuits Type 2 Type 8-C Pull-up P-ch enable Data P-ch IN/OUT Schmitt trigger input with hysteresis Output N-ch disable Type 5-H Pull-up P-ch enable Data P-ch IN/OUT Output N-ch disable Input enable User's Manual U13600EJ2V0UM00...
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Page 37: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The µ PD789046 Subseries can each access up to 64 Kbytes of memory space. Figures 3-1 and 3-2 show the memory maps. Figure 3-1. Memory Map ( µ µ µ µ PD789046) F F F F H Special Function Register 256 ×...
Page 38 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( µ µ µ µ PD78F9046) F F F F H Special Function Register 256 × 8 bits F F 0 0 H F E F F H Internal High-Speed RAM 512 × 8 bits F D 0 0 H F C F F H Unusable...
Page 39: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The µ PD789046 Subseries provide the following internal ROMs (or flash memory) containing the following capacities.
Page 40: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Each of the µ PD789046 Subseries is provided with a wide range of addressing modes to make memory manipulation as efficient as possible. A data memory area (FD00H to FFFFH) can be accessed using a unique addressing mode according to its use, such as a special function register (SFR).
Page 41 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Data Memory Addressing Modes ( µ µ µ µ PD78F9046) F F F F H Special Function Register (SFR) SFR Addressing 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H Short Direct Addressing...
Page 42: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µ PD789046 Subseries provide the following on-chip processor registers: 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer. Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 43 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt are disabled. When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with an interrupt mask flag for various interrupt sources.
Page 44 CHAPTER 3 CPU ARCHITECTURE Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-7. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10 SP9...
Page 45: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
Page 46: Special Function Register (Sfr)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function register (SFR) Unlike a general-purpose register, each special function register has a special function. It is allocated in the 256-byte area FF00H to FFFFH. The special function register can be manipulated, like the general-purpose register, with the operation, transfer, and bit manipulation instructions.
Page 47 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (1/2) Address Special Function Register (SFR) Name Symbol Number of Bits Manipulated Simultaneously After Reset 1 Bit 8 Bits 16 Bits Ο Ο − FF00H Port 0 Ο Ο − FF01H Port 1 Ο...
Page 48 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (2/2) Address Special Function Register (SFR) Name Symbol Number of Bits Manipulated Simultaneously After Reset 1 Bit 8 Bits 16 Bits − Ο − FF74H Transmission shift register 20 TXS20 SIO20 −...
Page 49: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 50: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CALL or BR...
Page 51: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) to branch. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed.
Page 52: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods (addressing) are available to specify the register and memory which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier Description...
Page 53: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal high- speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 54: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can also be accessed with short direct addressing.
Page 55: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] The general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 56: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces.
Page 57: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
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Page 59: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD789046 Subseries is provided with the ports shown in Figure 4-1. These ports are used to enable several types of control. Table 4-1 lists the functions of each port. These ports, while originally designed as digital input/output ports, have alternate functions, as summarized in Section 2.1.
Page 60 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Pin Name Function After Reset Alternate Function − P00 to P07 Port 0 Input 8-bit input/output port Can be set to either input or output in 1-bit units When used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (PU0).
Page 61: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports have the following hardware configuration. Table 4-2. Configuration of Port Parameter Configuration Control register Port mode registers (PMm: m = 0 to 4) Pull-up resistor option register 0 (PU0) Pull-up resistor option register B2 (PUB2) Port Total: 34 (CMOS input/output: 34) Pull-up resistor...
Page 62: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 This is an 8-bit I/O port with an output latch. Port 1 can be set to input or output mode in 1-bit units by using port mode register 1 (PM1). When the P10 to P17 pins are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (PU0).
Page 63: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 This is an 8-bit I/O port with output latches. Port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (PM2). For pins P20 to P27, on-chip pull-up resistors can be connected in 1-bit units by using pull- up resistor option register B2 (PUB2).
Page 64 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P21 PUB2 PUB21 P-ch PORT Output Latch P21/TxD20/ (P21) SO20 PM21 Alternate Function SS20 Chip Select Input Signal PUB2 : Pull-up resistor option register B2 : Port mode register : Port 2 read signal : Port 2 write signal User's Manual U13600EJ2V0UM00...
Page 65 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 and P24 to P26 PUB2 PUB22, P-ch PUB24 to PUB26 Alternate Function PORT Output Latch P22/RxD20/SI20 (P22, P24 to P26) P24/INTP0 P25/INTP1 P26/INTP2/CPT90 PM22, PM24 to PM26 PUB2 : Pull-up resistor option register B2 : Port mode register : Port 2 read signal : Port 2 write signal...
Page 66 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P23 PUB2 PUB23 P-ch Alternate Function PORT Output Latch P23/SS20 (P23) PM23 PUB2 : Pull-up resistor option register B2 : Port mode register : Port 2 read signal : Port 2 write signal User's Manual U13600EJ2V0UM00...
Page 67 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P27 PUB2 PUB27 P-ch Alternate Function PORT Output Latch P27/TO80/TI80 (P27) PM27 Alternate Function PUB2 : Pull-up resistor option register B2 : Port mode register : Port 2 read signal : Port 2 write signal User's Manual U13600EJ2V0UM00...
Page 68: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 This is a 2-bit I/O port with output latches. Port 3 can be set to input or output mode in 1-bit units by using port mode register 3 (PM3). When P30 and P31 are used as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 0 (PU0).
Page 69: Port 4
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 This is an 8-bit I/O port with output latches. Port 4 can be set to input or output mode in 1-bit units by using port mode register 4 (PM4). When P40 to P47 are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using the pull-up resistor option register 0 (PU0).
Page 70: Port Function Control Registers
CHAPTER 4 PORT FUNCTIONS 4.3 Port Function Control Registers The following two types of registers are used to control the ports. • Port mode registers (PM0 to PM4) • Pull-up resistor option registers (PU0 and PUB2) Port mode registers (PM0 to PM4) The port mode registers separately set each port bit to either input or output.
Page 71 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Format of Port Mode Register Symbol Address After Reset PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H PM31...
Page 72 CHAPTER 4 PORT FUNCTIONS Pull-up resistor option register B2 (PUB2) This register specifies whether an on-chip pull-up resistor connected to each pin of port 2 is used. The pin for which use of an on-chip pull-up resistor is specified by PUB2 can use a pull-up register internally, regardless of the setting of the port mode register.
Page 73: Operation Of Port Functions
CHAPTER 4 PORT FUNCTIONS 4.4 Operation of Port Functions The operation of a port differs depending on whether the port is set to input or output mode, as described below. 4.4.1 Writing to I/O port In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.
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Page 75: Chapter 5 Clock Generation Circuit
CHAPTER 5 CLOCK GENERATION CIRCUIT 5.1 Clock Generation Circuit Functions The clock generation circuit generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. • • • • Main system clock oscillator This circuit oscillates at 1.0 to 5.0 MHz.
Page 76 CHAPTER 5 CLOCK GENERATION CIRCUIT Figure 5-1. Block Diagram of Clock Generation Circuit Internal Bus Suboscillation Mode Register (SCKM) Subsystem 16-Bit Timer 90 Clock Oscillator Watch Timer Prescaler Clock for Peripheral Hardware Main System Prescaler Clock Oscillator Standby Wait CPU Clock Controller Controller STOP...
Page 77: Registers Controlling Clock Generation Circuit
CHAPTER 5 CLOCK GENERATION CIRCUIT 5.3 Registers Controlling Clock Generation Circuit The clock generation circuit is controlled by the following registers: • Processor clock control register (PCC) • Suboscillation mode register (SCKM) • Subclock control register (CSS) Processor clock control register (PCC) PCC selects the CPU clock and the ratio of division.
Page 78 CHAPTER 5 CLOCK GENERATION CIRCUIT Suboscillation mode register (SCKM) SCKM specifies whether to use a feedback resistor for the subsystem clock, and controls the oscillation of the clock. SCKM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SCKM to 00H. Figure 5-3.
Page 79: System Clock Oscillators
CHAPTER 5 CLOCK GENERATION CIRCUIT 5.4 System Clock Oscillators 5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the reversed signal to the X2 pin.
Page 80 CHAPTER 5 CLOCK GENERATION CIRCUIT Figure 5-7. Unacceptable Resonator Connections (1/2) (a) Wiring too long (b) Crossed signal line PORTn (n = 0 to 4) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High Current High Current Remark...
Page 81: Scaler
CHAPTER 5 CLOCK GENERATION CIRCUIT Figure 5-7. Unacceptable Resonator Connections (2/2) (e) Signal is extracted (f) Signal conductors of the main and subsystem clocks are parallel and near to each other XT2 and X1 wiring in parallel Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to the XT2 pin in series.
Page 82: Clock Generation Circuit Operation
CHAPTER 5 CLOCK GENERATION CIRCUIT 5.5 Clock Generation Circuit Operation The clock generation circuit generates the following clocks and controls operation modes of the CPU, such as standby mode: • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The operation of the clock generation circuit is determined by the processor clock control register (PCC), suboscillation mode register (SCKM), and subclock control register (CSS), as follows: (1.6 µ...
Page 83: Changing Setting Of System Clock And Cpu Clock
CHAPTER 5 CLOCK GENERATION CIRCUIT 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS).
Page 84: Switching Between System Clock And Cpu Clock
CHAPTER 5 CLOCK GENERATION CIRCUIT 5.6.2 Switching between system clock and CPU clock The following figure illustrates how the system clock and CPU clock switch. Figure 5-8. Switching between System Clock and CPU Clock RESET Interrupt Request Signal System Clock CPU Clock Slow Fast Operation...
Page 85: Chapter 6 16-Bit Timer
CHAPTER 6 16-BIT TIMER 6.1 16-Bit Timer Functions The 16-bit timer has the following functions. • Timer interrupt • Timer output • Buzzer output • Count value capture Timer interrupt An interrupt is generated when a count value and compare value match. Timer output Timer output can be controlled when a count value and compare value match.
Page 86 Figure 6-1. Block Diagram of 16-Bit Timer Internal Bus 16-Bit Timer Mode Control Register 90 (TMC90) TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 PM30 Output Latch TO90/P30 16-Bit Compare Register Flip-Flop TOD90 90 (CR90) Match INTTM90 Sync Circuit BZO90/P31 16-Bit Timer Counter 90 (TM90) CTP90/INTP2/ PM31...
Page 87 CHAPTER 6 16-BIT TIMER 16-bit compare register 90 (CR90) A value specified in CR90 is compared with the count in 16-bit timer counter 90 (TM90). If they match, an interrupt request (INTTM90) is issued by CR90. CR90 is set with an 8-bit or 16-bit memory manipulation instruction. Any value from 0000H to FFFFH can be set.
Page 88: Registers Controlling 16-Bit Timer
CHAPTER 6 16-BIT TIMER 6.3 Registers Controlling 16-Bit Timer The following three types of registers control the 16-bit timer. • 16-bit timer mode control register 90 (TMC90) • Buzzer output control register 90 (BZC90) • Port mode register 3 (PM3) 16-bit timer mode control register 90 (TMC90) 16-bit timer mode control register 90 (TMC90) controls the setting of a count clock, capture edge, etc.
Page 89 CHAPTER 6 16-BIT TIMER Figure 6-2. Format of 16-Bit Timer Mode Control Register 90 Symbol <6> <0> Address After Reset Note TMC90 FF48H TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TOD90 Timer Output Data Timer output of 0 Timer output of 1 TOF90 Overflow Flag Control Reset or cleared by software...
Page 90 CHAPTER 6 16-BIT TIMER Buzzer output control register 90 (BZC90) This register selects a buzzer frequency based on fcl selected with the count clock select bits (TCL901 and TCL900), and controls the output of a square wave. BZC90 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears BZC90 to 00H.
Page 91 CHAPTER 6 16-BIT TIMER Port mode register 3 (PM3) PM3 is used to set each bit of port 3 to input or output. When pin P30/TO90 is used for timer output, reset the output latch of P30 and PM30 to 0; when pin P31/BZO90 is used for buzzer output, reset the output latch of P31 and PM31 to 0.
Page 92: 16-Bit Timer Operation
CHAPTER 6 16-BIT TIMER 6.4 16-Bit Timer Operation 6.4.1 Operation as timer interrupt In the timer interrupt function, interrupts are repeatedly generated at the count value set in 16-bit compare register 90 (CR90) in advance based on the intervals of the value set in TCL901 and TCL900. To operate 16-bit timer as a timer interrupt, the following settings are required.
Page 93 CHAPTER 6 16-BIT TIMER Figure 6-6. Timing of Timer Interrupt Operation Count Clock TM90 Count Value 0000H 0001H FFFFH 0000H 0001H FFFFH CR90 INTTM90 Interrupt Accept Interrupt Accept TO90 TOF90 Overflow Flag Set Remark N = 0000H to FFFFH User's Manual U13600EJ2V0UM00...
Page 94: Operation As Timer Output
CHAPTER 6 16-BIT TIMER 6.4.2 Operation as timer output Timer outputs are repeatedly generated at the count value set in 16-bit compare register 90 (CR90) in advance based on the intervals of the value set in TCL901 and TCL900. To operate 16-bit timer as a timer output, the following settings are required. •...
Page 95: Capture Operation
CHAPTER 6 16-BIT TIMER 6.4.3 Capture operation The capture operation consists of latching the count value of 16-bit timer counter 90 (TM90) into a capture register synchronizing with a capture trigger, and retaining the count value. Set TMC90 as shown in Figure 6-9 to allow 16-bit timer to start the capture operation. Figure 6-9.
Page 96: 16-Bit Timer Counter 90 Readout
CHAPTER 6 16-BIT TIMER 6.4.4 16-bit timer counter 90 readout The count value of 16-bit timer counter 90 (TM90) is read out with a 16-bit manipulation instruction. TM90 readout is performed through a counter read buffer. The counter read buffer latches the TM90 count value.
Page 97: Buzzer Output Operation
CHAPTER 6 16-BIT TIMER 6.4.5 Buzzer output operation The buzzer frequency is set using buzzer output control register 90 (BZC90) based on the count clock selected with TCL901 and TCL900 of TMC90 (source clock). A square wave of the set buzzer frequency is output. Table 6-4 shows the buzzer frequency.
Page 98: Notes On 16-Bit Timer
CHAPTER 6 16-BIT TIMER 6.5 Notes on 16-Bit Timer The functions of the 16-bit timer that can be used differ depending on the selection of a count clock, operation of the CPU clock, oscillation status of the system clock, and the setting of BZOE90 (bit 0 of the buzzer output control register 90 (BZC90)).
Page 99 CHAPTER 6 16-BIT TIMER To stop oscillation of the main system clock to reduce the current consumption and release HALT mode by using the timer interrupt, make the following settings: Count clock : Subsystem clock CPU clock : Subsystem clock Main system clock : Stop oscillation BZOE90 : 1 (buzzer output enabled)
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Page 101: Chapter 7 8-Bit Timer/Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.1 Functions of 8-Bit Timer/Event Counter The 8-bit timer/event counter has the following functions: • Interval timer • External event counter • Square wave output • PWM output 8-bit interval timer When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at any time intervals set in advance.
Page 102: 8-Bit Timer/Event Counter Configuration
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.2 8-Bit Timer/Event Counter Configuration The 8-bit timer/event counter consists of the following items of hardware. Table 7-3. 8-Bit Timer/Event Counter Configuration Item Configuration 8 bits × 1 (TM80) Timer counter Compare register: 8 bits × 1 (CR80) Register Timer output 1 (TO80)
Page 103: 8-Bit Timer/Event Counter Control Registers
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.3 8-Bit Timer/Event Counter Control Registers The following two types of registers are used to control the 8-bit timer/event counter. • 8-bit timer mode control register 80 (TMC80) • Port mode register 2 (PM2) 8-bit timer mode control register 80 (TMC80) TMC80 determines whether to enable or disable 8-bit timer counter 80 (TM80), specifies the count clock for TM80, and controls the operation of the output control circuit of 8-bit timer/event counter.
Page 104 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Port mode register 2 (PM2) PM2 specifies whether each bit of port 2 is used for input or output. To use the TO80/P27/TI80 pin for timer output, the PM27 and P27 output latch must be reset to 0. PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 105: Operation Of 8-Bit Timer/Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4 Operation of 8-Bit Timer/Event Counter 7.4.1 Operation as interval timer The interval timer repeatedly generates an interrupt at time intervals specified by the count value set in 8-bit compare register 80 (CR80) in advance. To operate the 8-bit timer/event counter as an interval timer, the settings are required in the following sequence.
Page 106 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-4. Interval Timer Operation Timing Count Clock TM80 Count Value Clear Clear CR80 TCE80 Count Start INTTM80 Interrupt Accept Interrupt Accept TO80 Interval Time Interval Time Interval Time Interval time = (N + 1) × t Remark N = 00H to FFH User's Manual U13600EJ2V0UM00...
Page 107: Operation As External Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses input to the TI80/P27/TO80 pin by using 8-bit timer counter 80 (TM80). To operate the 8-bit timer/event counter as an external event counter, the settings are required in the following sequence.
Page 108: Operation As Square Wave Output
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.3 Operation as square wave output The 8-bit timer/event counter can generate output square waves of an arbitrary frequency at intervals specified by the count value set in 8-bit compare register 80 (CR80) in advance. To operate 8-bit timer/event counter 80 for square wave output, the settings are required in the following sequence.
Page 109 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-6. Square Wave Output Timing Count Clock TM80 Count Value Clear Clear CR80 TCE80 Count Start INTTM80 Interrupt Accept Interrupt Accept Note TO80 Note The initial value of TO80 is low for output enable (TOE80 = 1). User's Manual U13600EJ2V0UM00...
Page 110: Pwm Output Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.4 PWM output operation PWM output enables an interrupt to be generated repeatedly at intervals specified by the count value set in 8-bit compare register 80 (CR80) in advance. To use the 8-bit timer/event counter for PWM output, the following settings are required. <1>...
Page 111: Notes On Using 8-Bit Timer/Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.5 Notes on Using 8-Bit Timer/Event Counter Error on starting timer An error of up to 1 clock is included in the time between the timer being started and a coincidence signal being generated. This is because 8-bit timer counter 80 (TM80) is started asynchronously to the count pulse.
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Page 113: Chapter 8 Watch Timer
CHAPTER 8 WATCH TIMER 8.1 Watch Timer Functions The watch timer has the following functions: • Watch timer • Interval timer The watch and interval timers can be used at the same time. Figure 8-1 is a block diagram of the watch timer. Figure 8-1.
Page 114: Watch Timer Configuration
CHAPTER 8 WATCH TIMER Watch timer The 4.19-MHz main system clock or 32.768-kHz subsystem clock is used to issue an interrupt request (INTWT) at 0.5-second intervals. Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5- second interval.
Page 115: Watch Timer Control Register
CHAPTER 8 WATCH TIMER 8.3 Watch Timer Control Register The watch timer mode control register (WTM) is used to control the watch timer. • Watch timer mode control register (WTM) WTM selects a count clock for the watch timer and specifies whether to enable operation of the timer. It also specifies the prescaler interval and how the 5-bit counter is controlled.
Page 116: Watch Timer Operation
CHAPTER 8 WATCH TIMER 8.4 Watch Timer Operation 8.4.1 Operation as watch timer The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used to enable the watch timer to operate at 0.5-second intervals. The watch timer is used to generate an interrupt request at specified intervals. By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer starts counting.
Page 117 CHAPTER 8 WATCH TIMER Figure 8-3. Watch Timer/Interval Timer Operation Timing 5-Bit Counter Overflow Overflow Start Count Clock Watch Timer Interrupt INTWT Watch Timer Interrupt Time (0.5 s) Watch Timer Interrupt Time (0.5 s) Interval Timer Interrupt INTWTI Interval Timer (T) Remarks 1.
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Page 119: Chapter 9 Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.1 Watchdog Timer Functions The watchdog timer has the following functions: • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). Watchdog timer The watchdog timer is used to detect inadvertent program loops.
Page 120: Watchdog Timer Configuration
CHAPTER 9 WATCHDOG TIMER 9.2 Watchdog Timer Configuration The watchdog timer consists of the following items of hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control register Timer clock selection register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 9-1. Block Diagram of Watchdog Timer Internal Bus TMMK4 Prescaler...
Page 121: Watchdog Timer Control Registers
CHAPTER 9 WATCHDOG TIMER 9.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock selection register 2 (TCL2) • Watchdog timer mode register (WDTM) Timer clock selection register 2 (TCL2) This register sets the watchdog timer count clock.
Page 122 CHAPTER 9 WATCHDOG TIMER Watchdog timer mode register (WDTM) This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 9-3.
Page 123: Watchdog Timer Operation
CHAPTER 9 WATCHDOG TIMER 9.4 Watchdog Timer Operation 9.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock selection register 2 (TCL2).
Page 124: Operation As Interval Timer
CHAPTER 9 WATCHDOG TIMER 9.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance.
Page 125: Chapter 10 Serial Interface 20
CHAPTER 10 SERIAL INTERFACE 20 10.1 Serial Interface 20 Functions Serial interface 20 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode Operation stop mode This mode is used when serial transfer is not performed. Power consumption is minimized in this mode. Asynchronous serial interface (UART) mode This mode is used to send and receive the one byte of data that follows a start bit.
Page 126 Figure 10-1. Block Diagram of Serial Interface 20 Internal Bus Serial Operation Mode Asynchronous Serial Interface Asynchronous Serial Interface Register 20 (CSIM20) Status Register 20 (ASIS20) Mode Register 20 (ASIM20) Reception Buffer CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 PE20 FE20 OVE20 TXE20 RXE20 PS201 PS200 CL20 SL20 Register 20 (RXB20) Switching of the First Bit...
Page 127 Figure 10-2. Block Diagram of Baud Rate Generator 20 Reception Detection Clock Transmission Transmission Shift Clock Clock Counter Reception Shift Clock Reception Clock Counter TXE20 SCK20/ASCK20/P20 RXE20 CSIE20 Reception Detected TPS203 TPS202 TPS201 TPS200 Baud Rate Generator Control Register 20 (BRGC20) Internal Bus...
Page 128 CHAPTER 10 SERIAL INTERFACE 20 Transmission shift register 20 (TXS20) TXS20 is a register in which transmission data is prepared. The transmission data is output from TXS20 bit-serially. When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing data to TXS20 triggers transmission.
Page 129: Serial Interface 20 Control Registers
CHAPTER 10 SERIAL INTERFACE 20 10.3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the following registers. • Serial operation mode register 20 (CSIM20) • Asynchronous serial interface mode register 20 (ASIM20) • Asynchronous serial interface status register 20 (ASIS20) •...
Page 130 CHAPTER 10 SERIAL INTERFACE 20 Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set when serial interface 20 is used in asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Figure 10-4.
Page 131 CHAPTER 10 SERIAL INTERFACE 20 Table 10-2. Serial Interface 20 Operating Mode Settings Operation stop mode ASIM20 CSIM20 PM22 PM21 PM20 First Shift P22/SI20/ P21/SO20/ P20/SCK20/ Clock RxD20 Pin TxD20 Pin ASCK20 Pin TXE20 RXE20 CSIE20 DIR20 CSCK20 Function Function Function ×...
Page 132 CHAPTER 10 SERIAL INTERFACE 20 Asynchronous serial interface status register 20 (ASIS20) ASIS20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS20 are undefined in 3-wire serial I/O mode.
Page 133 CHAPTER 10 SERIAL INTERFACE 20 Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface 20. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Figure 10-6. Format of Baud Rate Generator Control Register 20 Symbol Address After Reset...
Page 134 CHAPTER 10 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the ASCK20 pin. (a) Generation of baud rate transmit/receive clock form system clock The transmit/receive clock is generated by scaling the system clock.
Page 135 CHAPTER 10 SERIAL INTERFACE 20 (b) Generation of baud rate transmit/receive clock from external clock input from ASCK20 pin The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input from the ASCK20 pin is estimated by using the following expression.
Page 136: Serial Interface 20 Operation
CHAPTER 10 SERIAL INTERFACE 20 10.4 Serial Interface 20 Operation Serial interface 20 provides the following three types of modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 10.4.1 Operation stop mode In operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. The P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O ports.
Page 137: Asynchronous Serial Interface (Uart) Mode
CHAPTER 10 SERIAL INTERFACE 20 10.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is possible. This device incorporates a UART-dedicated baud rate generator that enables communications at a desired baud rate from many options.
Page 138 CHAPTER 10 SERIAL INTERFACE 20 (a) Serial operation mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Set CSIM20 to 00H when UART mode is selected. Symbol <7> Address After Reset CSIM20...
Page 139 CHAPTER 10 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Symbol <7> <6> Address After Reset ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20...
Page 140 CHAPTER 10 SERIAL INTERFACE 20 (c) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIS20 to 00H. Symbol Address After Reset ASIS20 PE20 FE20 OVE20 FF71H PE20 Parity Error Flag Parity error not generated Parity error generated (when the parity of transmit data does not match)
Page 141 CHAPTER 10 SERIAL INTERFACE 20 (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Symbol Address After Reset BRGC20 TPS203 TPS202 TPS201 TPS200 FF73H TPS203 TPS202 TPS201 TPS200 3-Bit Counter Source Clock Selection...
Page 142 CHAPTER 10 SERIAL INTERFACE 20 Table 10-5. Example of Relationships between System Clock and Baud Rate Baud Rate (bps) BRGC20 Set Value Error (%) = 5.0 MHz = 4.9152 MHz 1,200 1.73 2,400 4,800 9,600 19,200 38,400 76,800 Caution Do not select n = 1 during operation at f = 5.0 MHz because the resulting baud rate exceeds the rated range.
Page 143 CHAPTER 10 SERIAL INTERFACE 20 Communication operation (a) Data format The transmit/receive data format is as shown in Figure 10-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s). The specification of character bit length in one data frame, parity selection, and specification of stop bit length is carried out with asynchronous serial interface mode register 20 (ASIM20).
Page 144 CHAPTER 10 SERIAL INTERFACE 20 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.
Page 145 CHAPTER 10 SERIAL INTERFACE 20 (c) Transmission A transmit operation is started by writing transmit data to transmission shift register 20 (TXS20). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a transmission completion interrupt (INTST20) is generated.
Page 146 CHAPTER 10 SERIAL INTERFACE 20 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set to 1, a receive operation is enabled and sampling of the RxD20 pin input is performed. RxD20 pin input sampling is performed using the serial clock specified by ASIM20. When the RxD20 pin input becomes low, the 3-bit counter starts counting, and at the time when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output.
Page 147 CHAPTER 10 SERIAL INTERFACE 20 (e) Receive errors The following three errors may occur during a receive operation: a parity error, framing error, and overrun error. After data reception, an error flag is set in asynchronous serial interface status register 20 (ASIS20).
Page 148 CHAPTER 10 SERIAL INTERFACE 20 Cautions related to UART mode (a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmission shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing the next transmission.
Page 149: 3-Wire Serial I/O Mode
CHAPTER 10 SERIAL INTERFACE 20 10.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous serial interface, such as the 75XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK20), serial output (SO20), and serial input (SI20).
Page 150 CHAPTER 10 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. When 3-wire serial I/O mode is selected, ASIM20 must be set to 00H. Symbol <7>...
Page 151 CHAPTER 10 SERIAL INTERFACE 20 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Symbol Address After Reset BRGC20 TPS203 TPS202 TPS201 TPS200 FF73H TPS203 TPS202 TPS201 TPS200 3-Bit Counter Source Clock Selection...
Page 152 CHAPTER 10 SERIAL INTERFACE 20 Communication operation In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Transmission shift register 20 (TXS20/SIO20) and reception shift register 20 (RXS20) shift operations are performed in synchronization with the fall of the serial clock (SCK20).
Page 153 CHAPTER 10 SERIAL INTERFACE 20 Figure 10-11. 3-Wire Serial I/O Mode Timing (2/7) (ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 SI20 SO20 Note INTCSI20 Note The value of the last bit previously output is output. (iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1) SS20 SIO20...
Page 154 CHAPTER 10 SERIAL INTERFACE 20 Figure 10-11. 3-Wire Serial I/O Mode Timing (3/7) (iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 SO20 SI20 INTCSI20 (v) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20...
Page 155 CHAPTER 10 SERIAL INTERFACE 20 Figure 10-11. 3-Wire Serial I/O Mode Timing (4/7) (vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1) SS20 SIO20 Write SCK20 Note 1 SIO20 Write (master) SI20 Hi-Z Hi-Z Note 2 SO20 INTCSI20 Notes 1.
Page 156 CHAPTER 10 SERIAL INTERFACE 20 Figure 10-11. 3-Wire Serial I/O Mode Timing (5/7) (viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 Note SIO20 Write (master) SI20 SO20 INTCSI20 Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20.
Page 157 CHAPTER 10 SERIAL INTERFACE 20 Figure 10-11. 3-Wire Serial I/O Mode Timing (6/7) (x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 SO20 Note SI20 INTCSI20 Note The value of the last bit previously output is output. (xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write...
Page 158 CHAPTER 10 SERIAL INTERFACE 20 Figure 10-11. 3-Wire Serial I/O Mode Timing (7/7) (xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1) SS20 SIO20 Write SCK20 SI20 Hi-Z Hi-Z Note 1 Note 2 SO20 INTCSI20 Notes 1. The value of the last bit previously output is output. 2.
Page 159: Chapter 11 Interrupt Functions
CHAPTER 11 INTERRUPT FUNCTIONS 11.1 Interrupt Function Types The following two types of interrupt functions are used. Non-maskable interrupt This interrupt is acknowledged unconditionally even if interrupts are disabled. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 160 CHAPTER 11 INTERRUPT FUNCTIONS Table 11-1. Interrupt Sources Note 1 Interrupt Type Priority Interrupt Source Internal/External Vector Table Basic Address Configuration Name Trigger Note 2 Type − Non-maskable INTWDT Watchdog timer overflow Internal 0004H interrupt (when watchdog timer mode 1 is selected) Maskable INTWDT...
Page 161 CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal Bus Vector Table Interrupt Request Address Generator Standby Release Signal (B) Internal maskable interrupt Internal Bus Vector Table Address Generator Interrupt Request Standby Release Signal (C) External maskable interrupt Internal Bus INTM0, KRM00...
Page 162: Interrupt Function Control Registers
CHAPTER 11 INTERRUPT FUNCTIONS 11.3 Interrupt Function Control Registers The interrupt functions are controlled by the following five registers: • Interrupt request flag registers 0 and 1 (IF0 and IF1) • Interrupt mask flag registers 0 and 1 (MK0 and MK1) •...
Page 163 CHAPTER 11 INTERRUPT FUNCTIONS Interrupt request flag registers 0 and 1 (IF0 and IF1) An interrupt request flag is set to 1, when the corresponding interrupt request is issued, or when the related instruction is executed. It is cleared to 0, when the interrupt request is accepted, when a RESET signal is input, or when a related instruction is executed.
Page 164 CHAPTER 11 INTERRUPT FUNCTIONS Interrupt mask flag registers 0 and 1 (MK0 and MK1) The interrupt mask flags are used to enable and disable the corresponding maskable interrupts. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 and MK1 to FFH.
Page 165 CHAPTER 11 INTERRUPT FUNCTIONS External interrupt mode register 0 (INTM0) INTM0 is used to specify an effective edge for INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Figure 11-4. Format of External Interrupt Mode Register 0 Symbol Address After Reset...
Page 166 CHAPTER 11 INTERRUPT FUNCTIONS Program status word (PSW) The program status word is used to hold the instruction execution result and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW. PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (EI and DI).
Page 167 CHAPTER 11 INTERRUPT FUNCTIONS Key return mode register 00 (KRM00) KRM00 is used to specify pins for which the key return signals are detected. KRM00 is set with a 1-bit or 8-bit memory manipulation instruction. Bit 0 (KRM000) specifies whether the detection is performed for four pins from KR00/P40 to KR03/P43 together.
Page 168: Interrupt Processing Operation
CHAPTER 11 INTERRUPT FUNCTIONS 11.4 Interrupt Processing Operation 11.4.1 Non-maskable interrupt request acceptance operation The non-maskable interrupt request is unconditionally accepted even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Page 169 CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-8. Flowchart from Non-Maskable Interrupt Request Generation to Acceptance Start WDTM4 = 1 (watchdog timer mode is selected) Interval Timer Overflows WDTM3 = 0 (non-maskable interrupt is selected) Reset Processing Interrupt request is generated Interrupt processing is started WDTM : Watchdog timer mode register : Watchdog timer Figure 11-9.
Page 170: Maskable Interrupt Request Acceptance Operation
CHAPTER 11 INTERRUPT FUNCTIONS 11.4.2 Maskable interrupt request acceptance operation A maskable interrupt request can be accepted when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is accepted in the interrupt enabled status (when the IE flag is set to 1).
Page 171 CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-11. Interrupt Request Acceptance Processing Algorithm Start ××IF = 1 ? Yes (Interrupt request generated) ××MK = 0 ? Interrupt Request Pending IE = 1 ? Interrupt Request Pending Vectored Interrupt Processing ××IF : Interrupt request flag ××MK : Interrupt mask flag : Flag to control maskable interrupt request acceptance (1 = enable, 0 = disable) User's Manual U13600EJ2V0UM00...
Page 172: Multiplexed Interrupt Processing
CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-12. Interrupt Request Acceptance Timing (Example of MOV A,r) 8 Clocks Clock Saving PSW and PC, Jump Interrupt Processing Program MOV A,r to Interrupt Processing Interrupt If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n − 1, the interrupt is accepted after the instruction under execution completes.
Page 173 CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-14. Example of Multiple Interrupt Example 1. A multiple interrupt is accepted INTxx Processing INTyy Processing Main Processing IE = 0 IE = 0 INTxx INTyy RETI RETI During interrupt INTxx servicing, interrupt request INTyy is accepted, and a multiple interrupt is generated. An EI instruction is issued before each interrupt request acceptance, and the interrupt request acceptance enable state is set.
Page 174: Interrupt Request Reserve
CHAPTER 11 INTERRUPT FUNCTIONS 11.4.4 Interrupt request reserve Some instructions may reserve the acceptance of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution.
Page 175: Chapter 12 Standby Function
CHAPTER 12 STANDBY FUNCTION 12.1 Standby Function and Configuration 12.1.1 Standby function The standby function is to reduce the power dissipation of the system and can be effected in the following two modes: HALT mode This mode is set when the HALT instruction is executed. HALT mode stops the operation clock of the CPU. The system clock oscillation circuit continues oscillating.
Page 176: Standby Function Control Register
CHAPTER 12 STANDBY FUNCTION 12.1.2 Standby function control register The wait time after STOP mode is released upon interrupt request until the oscillation settles is controlled with the oscillation settling time selection register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 177: Operation Of Standby Function
CHAPTER 12 STANDBY FUNCTION 12.2 Operation of Standby Function 12.2.1 HALT mode HALT mode HALT mode is set by executing the HALT instruction. The operation status in HALT mode is shown in the following table. Table 12-1. Operation Statuses in HALT Mode Item HALT Mode Operation Status While the Main HALT Mode Operation Status While the...
Page 178 CHAPTER 12 STANDBY FUNCTION Releasing HALT mode HALT mode can be released by the following three types of sources: (a) Releasing by unmasked interrupt request HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is enabled to be accepted, vectored interrupt processing is performed.
Page 179 CHAPTER 12 STANDBY FUNCTION (c) Releasing by RESET input When HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 12-3. Releasing HALT Mode by RESET Input Wait HALT : 6.55 ms)
Page 180: Stop Mode
CHAPTER 12 STANDBY FUNCTION 12.2.2 STOP mode Setting and operation status of STOP mode STOP mode is set by executing the STOP instruction. Caution Because standby mode can be released by an interrupt request signal, standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset.
Page 181 CHAPTER 12 STANDBY FUNCTION Releasing STOP mode STOP mode can be released by the following two types of sources: (a) Releasing by unmasked interrupt request STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is enabled to be accepted, vectored interrupt processing is performed, after the oscillation settling time has elapsed.
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Page 183: Chapter 13 Reset Function
CHAPTER 13 RESET FUNCTION The following two operations are available to generate reset signals. External reset input with RESET pin Internal reset by program run-away time detected with watchdog timer External and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by reset signal input.
Page 184 CHAPTER 13 RESET FUNCTION Figure 13-2. Reset Timing by RESET Input Reset Period Oscillation Normal Operation Normal Operation (oscillation Settling (reset processing) stops) Time Wait RESET Internal Reset Signal Delay Delay Hi-Z Port Pin Figure 13-3. Reset Timing by Overflow in Watchdog Timer Reset Period Oscillation Normal Operation...
Page 185 CHAPTER 13 RESET FUNCTION Table 13-1. State of the Hardware after a Reset Hardware State after Reset Note 1 Program counter (PC) Loaded with the contents of the reset vector table (0000H, 0001H) Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined...
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Page 187: Chapter 14 Μ Μ Μ Μ Pd78F9046
CHAPTER 14 µ µ µ µ PD78F9046 The µ PD78F9046 replaces the internal masked ROM of the µ PD789046 with flash memory. The differences between the flash memory and the masked ROM versions are shown in Table 14-1. Table 14-1. Differences between Flash Memory and Masked ROM Versions Item Flash Memory Masked ROM...
Page 188: Flash Memory Programming
CHAPTER 14 µ µ µ µ PD78F9046 14.1 Flash Memory Programming The on-chip program memory in the µ PD78F9046 is a flash memory. The flash memory can be written with the µ PD78F9046 mounted on the target system (on-board). Connect the dedicated flash writer (Flashpro III (part number: FL-PR3, PG-FP3)) to the host machine and target system to write the flash memory.
Page 189: Function Of Flash Memory Programming
CHAPTER 14 µ µ µ µ PD78F9046 14.1.2 Function of flash memory programming By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. Table 14-3 shows the major functions of flash memory programming. Table 14-3.
Page 190 CHAPTER 14 µ µ µ µ PD78F9046 Figure 14-3. Flashpro III Connection Example in UART Mode µ Flashpro III PD78F9046 Note RESET RESET RxD20 TxD20 Note n = 1, 2 Figure 14-4. Flashpro III Connection Example in Pseudo 3-Wire Mode (When P0 Is Used) µ...
Page 191: Setting Example With Flashpro Iii (Pg-Fp3)
CHAPTER 14 µ µ µ µ PD78F9046 14.1.4 Setting Example with Flashpro III (PG-FP3) When writing data to the flash memory by using the Flashpro III (PG-FP3), set as follows. <1> Load the parameter file. <2> Select a serial mode and serial clock by using the type command. <3>...
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Page 193: Chapter 15 Instruction Set
CHAPTER 15 INSTRUCTION SET This chapter lists the instruction set of the µ PD789046 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series User's Manual     Instruction (U11047E). 15.1 Operation 15.1.1 Operand identifiers and description methods Operands are described in "Operands"...
Page 194: Description Of "Operation" Column
CHAPTER 15 INSTRUCTION SET 15.1.2 Description of "Operation" column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair...
Page 195: Operation List
CHAPTER 15 INSTRUCTION SET 15.2 Operation List Mnemonic Operands Byte Clock Operation Flag AC CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte A ← r Note 1 A, r r ← A Note 1 r, A A ←...
Page 196 CHAPTER 15 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag AC CY rp ← word MOVW rp, #word AX ← (saddrp) AX, saddrp (saddrp) ← AX saddrp, AX AX ← rp Note AX, rp rp ← AX Note rp, AX AX ↔...
Page 197 CHAPTER 15 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag AC CY A, CY ← A − byte − CY × × × SUBC A, #byte (saddr), CY ← (saddr) − byte − CY × × × saddr, #byte A, CY ← A − r − CY ×...
Page 198 CHAPTER 15 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag AC CY A − byte × × × A, #byte (saddr) − byte × × × saddr, #byte A − r × × × A, r A − (saddr) × ×...
Page 199 CHAPTER 15 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag AC CY (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) CALL !addr16 PC ← addr16, SP ← SP − 2 (SP − 1) ← (PC + 1) , (SP −...
Page 200: Instructions Listed By Addressing Type
CHAPTER 15 INSTRUCTION SET 15.3 Instructions Listed by Addressing Type 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr !addr16 [DE] [HL] $addr16 None [HL + byte] 1st Operand Note...
Page 201 CHAPTER 15 INSTRUCTION SET 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word saddrp None 1st Operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, or HL. Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand...
Page 202 CHAPTER 15 INSTRUCTION SET Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic instructions CALL CALLT Compound instructions DBNZ Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User's Manual U13600EJ2V0UM00...
Page 203: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the µ PD789046 Subseries. Figure A-1 shows development tools. • Compatibility with PC98-NX Series Unless stated otherwise, products which are supported for the IBM PC/AT and compatibles can also be used with the PC98-NX Series.
Page 204 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Language Processing Software Embedded Software • Assembler Package • C Compiler Package • OS • System Simulator • Device File • C Compiler Source File • Integrated Debugger Host Machine (PC or EWS) Interface Adapter Flash Memory Writing Tools...
Page 205: Language Processing Software
APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K0S Program that converts program written in mnemonic into object code that can be executed by Assembler package microcontroller. In addition, automatic functions to generate symbol table and optimize branch instructions are also provided.
Page 206: Flash Memory Writing Tools
APPENDIX A DEVELOPMENT TOOLS A.2 Flash Memory Writing Tools Flashpro III Flash writer dedicated to the microcontrollers incorporating a flash memory. (part number: FL-PR3, PG-FP3) Flash writer FA-44GB-8ES Flash memory writing adapter. Used in connection with Flashpro III. • FA-44GB-8ES: For 44-pin plastic LQFP (GB-8ES type) Flash memory writing adapter Remark FL-PR3 and FA-44GB-8ES are products of Naito Densei Machida Mfg.
Page 207: Software
APPENDIX A DEVELOPMENT TOOLS A.3.2 Software ID78K0S-NS Control program for debugging the 78K/0S Series. Integrated debugger This program provides a graphical user interface. It runs on Windows for personal computer (Supports in-circuit emulator users and on OSF/Motif for engineering work station users, and has visual designs and IE-78K0S-NS) operability that comply with these operating systems.
Page 208: Conversion Socket (Ev-9200G-44) Drawing And Recommended Footprint
APPENDIX A DEVELOPMENT TOOLS A.4 Conversion Socket (EV-9200G-44) Drawing and Recommended Footprint Figure A-2. EV-9200G-44 Package Drawing (Reference) (unit: mm) Based on EV-9200G-44 (1) Package drawing (in mm) EV-9200G-44 No.1 pin index EV-9200G-44-G0E ITEM MILLIMETERS INCHES 15.0 0.591 10.3 0.406 10.3 0.406 15.0...
Page 209 APPENDIX A DEVELOPMENT TOOLS Figure A-3. EV-9200G-44 Footprints (Reference) (unit: mm) Based on EV-9200G-44 (2) Pad drawing (in mm) EV-9200G-44-P1E ITEM MILLIMETERS INCHES 15.7 0.618 11.0 0.433 0.8 ± 0.02 × 10=8.0 ± 0.05 × 0.394=0.315 +0.002 +0.002 0.031 –0.001 –0.002 0.8 ±...
Page 210: Conversion Adapter (Tgb-044Sap) Drawing
APPENDIX A DEVELOPMENT TOOLS A.5 Conversion Adapter (TGB-044SAP) Drawing Figure A-4. TGB-044SAP Package Drawing (Reference) (unit: mm) Reference diagram: TGB-044SAP (TQPACK044SA+TQSOCKET044SAP) Package dimension (unit: mm) Protrusion height ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES 10.12 0.398 0.079 0.8x10=8.0 0.031x0.394=0.315 0.25 0.010 0.031 0.378 16.65...
Page 211: Appendix B Embedded Software
APPENDIX B EMBEDDED SOFTWARE The following embedded software products are available for efficient program development and maintenance of the µ PD789046 Subseries. MX78K0S is a subset OS that is based on the µ ITRON specification. Supplied with the MX78K0S MX78K0S nucleus. The MX78K0S OS controls tasks, events, and time. In task control, the MX78K0S OS controls task execution order, and performs the switching process to a task to be executed.
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Page 213: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Name Index (Alphabetic Order) 16-bit capture register 90 (TCP90) ........................87 16-bit compare register 90 (CR90) ........................87 16-bit timer counter 90 (TM90) ..........................87 16-bit timer mode control register 90 (TMC90)...................... 88 8-bit compare register 80 (CR80) ........................102 8-bit timer counter 80 (TM80) ..........................
Page 214 APPENDIX C REGISTER INDEX Port mode register 4 (PM4) ............................70 Processor clock control register (PCC) ........................77 Pull-up resistor option register 0 (PU0) ........................71 Pull-up resistor option register B2 (PUB2)......................72 Reception buffer register 20 (RXB20) ........................128 Serial operation mode register 20 (CSIM20) ................129, 136, 138, 149 Subclock control register (CSS) ..........................78 Suboscillation mode register (SCKM)........................78 Timer clock selection register 2 (TCL2)........................121...
Page 215: Register Symbol Index (Alphabetic Order)
APPENDIX C REGISTER INDEX C.2 Register Symbol Index (Alphabetic Order) ASIM20 : Asynchronous serial interface mode register 20........... 130, 136, 139, 150 ASIS20 : Asynchronous serial interface status register 20 ..............132, 140 BRGC20 : Baud rate generator control register 20 ................ 133, 141, 151 BZC90 : Buzzer output control register 90....................
Page 216 APPENDIX C REGISTER INDEX SCKM : Suboscillation mode register......................78 TCL2 : Timer clock selection register 2 .....................121 TCP90 : 16-bit capture register 90.........................87 TM80 : 8-bit timer counter 80........................102 TM90 : 16-bit timer counter 90........................87 TMC80 : 8-bit timer mode control register 80 ....................103 TMC90 : 16-bit timer mode control register 90 ....................88 TXS20...
Page 217: Appendix D Revision History
APPENDIX D REVISION HISTORY The revision history for this manual is detailed below. "Chapter" indicates the chapter of the edition. Edition Revision from Previous Edition Chapter Completion of development of µ PD789046 and µ PD78F9046 Second edition Throughout Change of recommended connection of unused pins in processing of CHAPTER 2 PIN FUNCTIONS input/output circuit type of each pin and unused pins Correction of 16-bit timer block diagram...
Page 218 [MEMO] User's Manual U13600EJ2V0UM00...
Page 219 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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