Table 69 Ddrc_Lpr_Queue_Param_2_Cr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 68 • DDRC_LPR_QUEUE_PARAM_1_CR (continued)
Bit
Number Name
[3:0] REG_DDRC_LPR_XACT_RUN_LENGTH
Table 69 • DDRC_LPR_QUEUE_PARAM_2_CR
Bit
Number Name
[31:16] Reserved
[10:0] REG_DDRC_LPR_MAX_STARVE_X32
Table 70 • DDRC_WR_QUEUE_PARAM_CR
Bit
Number Name
[31:15] Reserved
[14:4] REG_DDRC_W_MIN_NON_CRITICAL
[3:0] REG_DDRC_W_XACT_RUN_LENGTH
Table 71 • DDRC_PERF_PARAM_2_CR
Bit
Number Name
[31:12] Reserved
11 REG_DDRC_BURSTCHOP
Microsemi Proprietary UG0446 User Guide Revision 7.0
Reset
Value Description
0×0 Number of transactions that are serviced once
the LPR queue goes critical is the smaller of this
value and number of transactions available.
Units: Transactions.
Reset
Value Description
0×0 Software should not rely on the value of a
reserved bit. To provide compatibility with future
products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0 12 bits are split into two registers.
[11:1] bits of
REG_DDRC_HPR_MAX_STARVE_X32.
Number of clocks that the LPR queue can be
starved before it goes critical. Unit: 32 clocks.
Reset
Value Description
0×0 Software should not rely on the value of a
reserved bit. To provide compatibility with future
products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0 Number of clocks that the write queue is
guaranteed to be non-critical. Unit: 32 clocks.
0×0 Number of transactions that are serviced once
the WR queue goes critical is the smaller of this
value and number of transactions available.
Units: Transactions.
Reset
Value Description
0×0 Software should not rely on the value of a
reserved bit. To provide compatibility with future
products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0 Not supported in this version of the DDRC
controller always reads as zero.
87