Table 98 Ddrc_Lcb_Mask_3_Sr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 97 • DDRC_LCB_MASK_2_SR
[15:0] DDRC_LCB_MASK
Table 98 • DDRC_LCB_MASK_3_SR
Bit
Number Name
[31:16] Reserved
[15:0] DDRC_LCB_MASK
Table 99 • DDRC_LCB_MASK_4_SR
Bit
Number Name
[31:16] Reserved
0×0 64 bits are split into four registers.
[31:16] bits of DDRC_LCB_MASK.
Indicates the mask of the corrected data.
1: On any bit indicates that the bit has been corrected by the DRAM
SECDED logic.
0: On any bit indicates that the bit has NOT been corrected by the
DRAM SECDED logic.
Valid when any bit of DDRC_REG_ECC_CORRECTED_ERR is High.
This mask does not indicate any correction that has been made in the
SECDED check bits.
If there are errors in multiple lanes, this signal will have the mask for the
lowest lane.
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0 64 bits are split into four registers.
[47:32] bits of DDRC_LCB_MASK.
Indicates the mask of the corrected data.
1: On any bit indicates that the bit has been corrected by the DRAM
SECDED logic.
0: On any bit indicates that the bit has NOT been corrected by the
DRAM SECDED logic.
Valid when any bit of DDRC_REG_ECC_CORRECTED_ERR is High.
This mask does not indicate any correction that has been made in the
SECDED check bits.
If there are errors in multiple lanes, this signal will have the mask for the
lowest lane.
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit
should be preserved across a read-modify-write operation.
Microsemi Proprietary UG0446 User Guide Revision 7.0 101