Design Flow Using Smartdesign; Figure 108 Fddr Clock Configuration - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
Figure 108 • FDDR Clock Configuration
4.10.2

Design Flow Using SmartDesign

The following illustration shows the design flow for using the FDDR subsystem to access external DDR
memory.
The design flow consists of two parts:
• Libero flow: This includes configuring the type of DDR memory, choosing fabric master interface
type, clocking, and DDR I/O settings.
• FDDR register initialization: FDDR subsystem registers can be initialized using the ARM Cortex-
M3 processor or FPGA fabric master. After MSS reset, the FDDR registers have to be configured
according to application and DDR memory specification. The
Configuration" section on page 152
features. While configuring the registers, the soft reset to the DDR controller must be asserted. After
releasing the soft reset, the DDR controller performs DDR memory initialization and sets the status
bits in DDRC_SR.
provides the details of required register configuration for FDDR
Microsemi ProprietaryUG0446 User Guide Revision 7.0
"FDDR Subsystem Features
192