Figure 6 Ddr Controller Block Diagram - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 10 • Priority Level Configuration
Writes from DSG bus
Writes from HPDMA/AHB bus
Writes from Fabric master having
the ID as PRIORITY_ID
IGLOO2
Reads from HPDMA/AHB bus
Reads from Fabric master having
the ID as PRIORITY_ID
Writes from HPDMA/AHB bus
Writes from Fabric master having
the ID as PRIORITY_ID
3.5.4.2.3 Transaction Handler
The transaction handler converts AXI transactions into DDR controller commands. The transaction
handler works on one transaction at a time from the read/write port queue that is selected by the priority
block.
The transaction handler has a write command controller and read command controller for write and read
transactions.
The write command controller fetches the command from the AXI slave write port and sends a pure write
instruction to the DDR controller. If SECDED is enabled, a read modified write (RMW) instruction is sent
to the DDR controller.
The read command controller generates read transactions to the DDR controller.
3.5.4.2.4 Reorder Buffer
The reorder buffer receives data from the DDR controller and orders the data as requested by the AXI
master when a single AXI transaction is split into multiple DDR controller transactions, depending on the
transfer size.
3.5.4.3 DDR Controller
The DDR controller receives requests from the AXI transaction controller, performs the address mapping
from system addresses to DRAM addresses (rank, bank, row, and column), and prioritizes requests to
minimize the latency of reads (especially high priority reads) and maximize page hits. It also ensures that
DRAM is properly initialized, all requests are made to DRAM legally (accounting for associated DRAM
constraints), refreshes are inserted as required, and the DRAM enters and exits various power-saving
modes appropriately. The following illustration shows the DDR controller connections in the MDDR
subsystem.
Figure 6 • DDR Controller Block Diagram
AXI
Transaction
Controller
16-Bit APB
Register Interface
The following sections describe key functions of the DDR controller.
5 5
6 7
7 6
PRIORITY_ENABLE_BIT=01/10/11 (Type-1/2/3)
1
2
3
4
DDR Controller
Microsemi Proprietary UG0446 User Guide Revision 7.0
5
7
6
2
1
4
3
Data
Interface
Control
PHY
Interface
Training
Interface
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