Microchip Technology Microsemi SmartFusion2 User Manual page 75

MDDR Subsystem
Table 28 • DDR Controller Configuration Register (continued)
Register Name
DDRC_DRAM_MR_TIMING_PARAM_CR
DDRC_DRAM_RAS_TIMING_CR
DDRC_DRAM_RD_WR_TRNARND_TIME_CR
DDRC_DRAM_T_PD_CR
DDRC_DRAM_BANK_ACT_TIMING_CR
DDRC_ODT_PARAM_1_CR
DDRC_ODT_PARAM_2_CR
DDRC_ADDR_MAP_COL_3_CR
DDRC_MODE_REG_RD_WR_CR
DDRC_MODE_REG_DATA_CR
DDRC_PWR_SAVE_1_CR
DDRC_PWR_SAVE_2_CR
DDRC_ZQ_LONG_TIME_CR
DDRC_ZQ_SHORT_TIME_CR
DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR
DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR
DDRC_PERF_PARAM_1_CR
DDRC_HPR_QUEUE_PARAM_1_CR
DDRC_HPR_QUEUE_PARAM_2_CR
DDRC_LPR_QUEUE_PARAM_1_CR
DDRC_LPR_QUEUE_PARAM_2_CR
Addres
s Offset
0×05C
0×060
0×064
0×068
0×06C
0×070
0×074
0×078
0×07C
0×080
0×084
0×088
0×08C
0×090
0×094
0×098
0×09C
0×0A0
0×0A4
0×0A8
0×0AC
Microsemi Proprietary UG0446 User Guide Revision 7.0
Registe Reset
r Type Source Description
RW PRESET_N DDRC DRAM Mode
Register Timing Parameter
register
RW PRESET_N DDRC DRAM RAS Timing
Parameter register
RW PRESET_N DDRC DRAM Read Write
Turn-around Timing register
RW PRESET_N DDRC DRAM Power-Down
Parameter register
RW PRESET_N DDRC DRAM Bank Activate
Timing Parameter register
RW PRESET_N DDRC ODT Delay Control
register
RW PRESET_N DDRC ODT Hold/Block
cycles register
RW PRESET_N Upper byte is DDRC
Column Address Map
register and lower byte
controls debug features.
RW PRESET_N DDRC Mode Register
Read/ Write Command
register
RW PRESET_N DDRC Mode Register Write
Data Register
RW PRESET_N DDRC Power Save register
RW PRESET_N DDRC Power Save register
RW PRESET_N DDRC ZQ Long Time
Calibration register
RW PRESET_N DDRC ZQ Short Time
Calibration register
RW PRESET_N DDRC ZQ Short Time
Calibration register
RW PRESET_N DDRC ZQ Short Time
Calibration register
RW PRESET_N DDRC Performance
Parameter register
RW PRESET_N DDRC Performance
Parameter register
RW PRESET_N DDRC Performance
Parameter register
RW PRESET_N DDRC Performance
Parameter register
RW PRESET_N DDRC Performance
Parameter register
64