Download
Share
Print this page
Microchip Technology Microsemi DDR AXI4 Arbiter User Manual
  1. Manuals
  2. Brands
  3. Microchip Technology Manuals
  4. Recording Equipment
  5. Microsemi DDR AXI4 Arbiter
  6. User manual
Microchip Technology Microsemi DDR AXI4 Arbiter User Manual

Microchip Technology Microsemi DDR AXI4 Arbiter User Manual

Hide thumbs

Advertisement

Quick Links

Download this manual
UG0950
User Guide
DDR_AXI4_Arbiter

Advertisement

loading
Need help?

Need help?

Do you have a question about the Microsemi DDR AXI4 Arbiter and is the answer not in the manual?

Questions and answers

Related Manuals for Microchip Technology Microsemi DDR AXI4 Arbiter

Summary of Contents for Microchip Technology Microsemi DDR AXI4 Arbiter

  • Page 1 UG0950 User Guide DDR_AXI4_Arbiter...
  • Page 2 About Microsemi ©2022 Microsemi, a wholly owned Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of subsidiary of Microchip Technology Inc. All semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets.
  • Page 3 1 Revision History ........... . . 1 Revision 2.0 .
  • Page 4 Figure 1 Top-level pin-out block diagram for Native Arbiter Interface ....... 3 Figure 2 Top-level block diagram for Arbiter Bus Interface .
  • Page 5 Table 1 Input and Output Ports for Arbiter Bus Interface ........4 Table 2 Input and Output ports for Native Arbiter Interface .

  • Page 6: Revision History

    Revision History Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. Revision 2.0 • Added Figure 2, page 4. • Added Table 1, page 4.

  • Page 7: Key Features

    Introduction Introduction Memories are an integral part of any typical video and graphics application. They are used for buffering video pixel data. One common buffering example displays frame buffers in which the complete video pixel data for a frame is buffered in the memory. Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is one of the commonly used memories in video applications for buffering.

  • Page 8: Hardware Implementation

    Hardware Implementation Hardware Implementation Design Description The DDR AXI4 Arbiter provides an AXI4 master interface to the DDR on-chip controllers. The arbiter supports up to eight write channels and eight read channels. The block arbitrates between eight read channels to provide access to the AXI read channel in a first-come first-serve manner. The same way the block arbitrates between eight write channels to provide access to the AXI write channel in a first-come first-serve manner.

  • Page 9: Inputs And Outputs

    Hardware Implementation Figure 2 • Top-level block diagram for Arbiter Bus Interface reset_i sys_clk_i ddr_ctrl_ready_i Write_channel_0 Write_channel_1 MIRRORED_SLAVE_AXI4 ARBITER IP Write_channel_7 Read_channel_0 Read_channel_1 Read_channel_7 A read transaction is triggered by setting the input signal r(x)_req_i high on a particular read channel. The arbiter responds by acknowledgment when it is ready to service the read request.
  • Page 10 Hardware Implementation Table 1 • Input and Output Ports for Arbiter Bus Interface SIGNAL NAME DIRECTION WIDTH DESCRIPTION ARADDR_I_0 Input [31:0] DDR address from where read has to be started for read channel 0 ARREADY_O_0 OutputOutp Arbiter acknowledgment to read request from read channel 0 RVALID_O_0 Output...
  • Page 11 Hardware Implementation Table 1 • Input and Output Ports for Arbiter Bus Interface SIGNAL NAME DIRECTION WIDTH DESCRIPTION ARADDR_I_4 Input [31:0] DDR address from where read has to be started for read channel 4 ARREADY_O_4 Output Arbiter acknowledgment to read request from read channel 4 RVALID_O_4 Output...
  • Page 12 Hardware Implementation Table 1 • Input and Output Ports for Arbiter Bus Interface SIGNAL NAME DIRECTION WIDTH DESCRIPTION WVALID_I_0 Input Write data valid to write channel 0 AWVALID_I_0 Input Write request from write channel 0 AWADDR_I_0 Input [31:0] DDR address to which write has to be happen from write channel 0 AWREADY_O_0 Output...
  • Page 13 Hardware Implementation Table 1 • Input and Output Ports for Arbiter Bus Interface SIGNAL NAME DIRECTION WIDTH DESCRIPTION AWREADY_O_4 Output Arbiter acknowledgment to write request from write channel 4 BUSER_O_4 Output Write completion to write channel 4 AWSIZE_I_5 Input 8 bits Write burst size for write channel 5 WDATA_I_5 Input...
  • Page 14 Hardware Implementation Table 2 • Input and Output ports for Native Arbiter Interface (continued) Signal Name Direction Width Description r0_rstart_addr_i Input 32 bits DDR address from where read has to be started for read channel 0 r0_ack_o Output Arbiter acknowledgment to read request from master 0 r0_data_valid_o Output...
  • Page 15 Hardware Implementation Table 2 • Input and Output ports for Native Arbiter Interface (continued) Signal Name Direction Width Description r5_rstart_addr_i Input 32 bits DDR address from where read has to be started for read channel 5 r5_ack_o Output Arbiter acknowledgment to read request from master 5 r5_data_valid_o Output...
  • Page 16 Hardware Implementation Table 2 • Input and Output ports for Native Arbiter Interface (continued) Signal Name Direction Width Description w2_burst_size_i Input 8 bits Write burst size w2_data_i Input [AXI_DATA_WIDTH - 1:0] Video data input to write channel 2 w2_data_valid_i Input Write data valid to write channel 2 w2_req_i Input...
  • Page 17 Hardware Implementation Table 2 • Input and Output ports for Native Arbiter Interface (continued) Signal Name Direction Width Description w6_wstart_addr_i Input 32 bits DDR address to which write has to be happen from write channel 6 w6_ack_o Output Arbiter acknowledgment to write request from master 6 w6_done_o Output...
  • Page 18 Hardware Implementation Table 2 • Input and Output ports for Native Arbiter Interface (continued) Signal Name Direction Width Description arready_o Input Read address ready. The slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready Read Data Channel Input...
  • Page 19 Hardware Implementation Table 2 • Input and Output ports for Native Arbiter Interface (continued) Signal Name Direction Width Description awcache Output [3:0] Cache type. Indicates the bufferable, cacheable, write-through, write-back, and allocate attributes of the transaction. Fixed to 4’b0000 à Non-cacheable and non- bufferable.

  • Page 20: Configuration Parameters

    Hardware Implementation Table 2 • Input and Output ports for Native Arbiter Interface (continued) Signal Name Direction Width Description bready Output Response ready. Master can accept the response information. 1 = master ready 0 = master not ready Configuration Parameters The following table lists the configuration parameters used in the hardware implementation of the DDR AXI4 Arbiter.

  • Page 21: Timing Diagram

    Hardware Implementation Timing Diagram The following figure shows the connection of the read and write request inputs, starting memory address, write inputs from the external master, read or write acknowledgment, and read or write completion inputs given by arbiter. Figure 3 • Timing Diagram for Signals used in Writing/Reading through AXI4 Interface The following figure shows the connection between the write data input from the external master along with the data input valid.
  • Page 22 License License The IP can be used in RTL mode without any license. Microsemi Proprietary UG0950 Revision 2.0...

  • Page 23: Installation Instructions

    Installation Instructions Installation Instructions The core must be installed into Libero software. It is done automatically through the Catalog update function in Libero, or the CPZ file can be manually added using the Add Core catalog feature. Once the CPZ file is installed in Libero, the core can be configured, generated, and instantiated within SmartDesign for inclusion in the Libero project.

  • Page 24: Resource Utilization

    Resource Utilization Resource Utilization ® DDR AXI4 Arbiter block is implemented on a PolarFire FPGA (MPF300T -1FCG1152E package) for four write channels and four read channels configuration. Table 4 • Resource utilization Resource Usage DFFs 2822 4 input LUTs 2999 MACC LSRAM 18K uSRAM 1K...