MDDR Subsystem
Table 109 • DDR_FIC_HPD_SW_RW_INVAL_CR (continued)
Bit
Number
Name
3
Reserved
2
DDR_FIC_flshM2
1
Reserved
0
DDR_FIC_invalid_M2
Table 110 • DDR_FIC_SW_WR_ERCLR_CR
Bit
Number
Name
[31:9]
Reserved
8
DDR_FIC_LTO_CLR
[7:5]
Reserved
4
DDR_FIC_M2_WR_ERCLR
[3:1]
Reserved
0
DDR_FIC_M1_WR_ERCLR
Table 111 • DDR_FIC_ERR_INT_ENABLE
Bit
Number
Name
[31:2]
Reserved
Reset
Value
Description
0×0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0
1: Flush write buffer for AHBL master2.
0: Default
0×0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0
1: Invalidate read buffer for AHBL master2.
0: Default
Reset
Value
Description
0×0
Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
0×0
Clear signal to lock timeout interrupt.
0×0
Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
0×0
Clear bit for error status of AHBL master2 write buffer. Once it
goes High, error status is cleared.
0×0
Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
0×0
Clear bit for error status posted by AHBL master1 write buffer.
Once it goes High, error status is cleared.
Reset
Value
Description
0×0
Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
Microsemi Proprietary UG0446 User Guide Revision 7.0
107
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