Table 61 Ddrc_Zq_Long_Time_Cr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 61 • DDRC_ZQ_LONG_TIME_CR
Bit
Number Name
[31:10] Reserved
[9:0] REG_DDRC_T_ZQ_LONG_NOP
Table 62 • DDRC_ZQ_SHORT_TIME_CR
Bit
Number Name
[31:10] Reserved
[9:0] REG_DDRC_T_ZQ_SHORT_NOP 0×0
Table 63 • DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR
Bit
Number Name
[31:16] Reserved
[15:4] REG_DDRC_T_ZQ_SHORT_INTERVAL_X1024
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
0×0 Number of cycles of NOP required after a ZQCL (ZQ
calibration long) command is issued to DRAM. Units: Clock
cycles.
This is only present for implementations supporting DDR3
devices
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
Number of cycles of NOP required after a ZQCS (ZQ
calibration short) command is issued to DRAM. Units: Clock
cycles.
This is only present for implementations supporting DDR3
devices.
Microsemi Proprietary UG0446 User Guide Revision 7.0
Reset
Value Description
0×0 Software should not rely on the value of a
reserved bit. To provide compatibility with
future products, the value of a reserved bit
should be preserved across a read-modify-
write operation.
0×0 20 bits are split into two registers.
[11:0] bits of
REG_DDRC_T_ZQ_SHORT_INTERVAL_
X1024.
Average interval to wait between automatically
issuing ZQ calibration short (ZQCS)
commands to DDR3 devices. Not considered if
REG_DDRC_DIS_AUTO_ZQ = 1. Units: 1,024
clock cycles
This is only present for implementations
supporting DDR3 devices.
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