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Microchip Technology Microsemi SmartFusion2 Manuals
Manuals and User Guides for Microchip Technology Microsemi SmartFusion2. We have
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Microchip Technology Microsemi SmartFusion2 manual available for free PDF download: User Manual
Microchip Technology Microsemi SmartFusion2 User Manual (240 pages)
FPGA High Speed DDR Interfaces
Brand:
Microchip Technology
| Category:
Recording Equipment
| Size: 8 MB
Table of Contents
Table of Contents
3
1 Revision History
12
Revision 7.0
12
Revision 6.0
12
Revision 5.0
12
Revision 4.0
12
Revision 3.0
12
Revision 2.0
12
Revision 1.0
13
Revision 0.0
13
2 Overview
14
Contents
14
Additional Documentation
14
Table 1 Additional Documents
14
3 MDDR Subsystem
16
Features
16
Memory Configurations
17
Figure 1 System Level MDDR Block Diagram
17
Performance
18
I/O Utilization
18
Table 2 Supported Memory (DDR2, DDR3 and LPDDR1) Configurations
18
Table 3 DDR Speeds
18
Table 4 I/O Utilization for Smartfusion2 and IGLOO2 Devices
18
Functional Description
19
Architecture Overview
19
Figure 2 MDDR Subsystem Functional Block Diagram
19
Port List
20
Table 5 MDDR Subsystem Interface Signals
20
Table 6 AXI Slave Interface Signals
22
Table 7 AHB Slave Interface Signals
25
Table 8 MDDR APB Slave Interface Signals
26
Initialization
27
Figure 3 Reset Sequence
28
Details of Operation
29
Figure 4 DDR_FIC Block Diagram
29
Table 9 MDDR_CLK to FPGA Fabric Clock Ratios
30
Figure 5 AXI Transaction Controller Block Diagram
31
Table 10 Priority Level Configuration
31
Figure 6 DDR Controller Block Diagram
32
Figure 7 DDR RMW Operation (32-Bit DDR Bus Width and Burst Length 8)
34
Figure 8 DDR RMW Operation (16-Bit DDR Bus Width and Burst Length 8)
34
Figure 9 DDR RMW Operation (8-Bit DDR Bus Width and Burst Length 8)
34
Table 11 SECDED DQ Lines at DDR
35
MDDR Subsystem Features Configuration
36
Table 12 Supported Bus Widths
36
Table 13 Supported Burst Modes
37
Table 14 Dynamically Enforced Bank Constraints
37
Table 15 Dynamically-Enforced Bank Constraints
38
Table 16 Dynamic DRAM Global Constraints
38
Figure 10 Address Mapping
39
Table 29 DDRC_DYN_SOFT_RESET_CR
41
Table 17 DDR Memory Regions
42
Table 18 Accessed DDR Memory Regions (Based on Mode Settings for 4 GB Memory)
42
How to Use MDDR in IGLOO2 Device
43
Table 19 Accessed DDR Memory Regions Based on Mode Settings for a 2 GB Memory
43
Table 20 Accessed DDR Memory Regions Based on Mode Settings for a 1 GB Memory
43
Configuring MDDR
44
Figure 11 System Builder-Device Features Window
44
Figure 12 MDR Initialization Path
45
Table 21 Supported Address Width Range for Row, Bank and Column Addressing in DDR/LPDDR
46
Table 22 DDR I/O Standard Is Configured Based on I/O Drive Strength Setting
46
Figure 13 I/O Drive Strength Setting
47
Figure 14 Selecting I/O Standard as LVCMOS18 or LPDDRI
48
Figure 15 Memory Initialization Configuration
50
Figure 16 Memory Timing Configuration
51
Figure 17 System Builder - Peripherals Tab
52
Figure 18 MDDR_CLK Configuration
53
Figure 19 DDR_FIC_CLK Configuration
53
Accessing MDDR from FPGA Fabric through the AXI Interface
54
Figure 20 I/O Editor Window
54
Figure 21 MDDR with AXI Interfaces
55
Figure 22 System Builder - Device Features Tab
56
Figure 23 Memory Configuration
56
Figure 24 Peripherals Tab with the Master Added and Configure Icon Highlighted
57
Figure 25 AMBA Master Configuration
57
Figure 26 System Clocks Configuration
58
Accessing MDDR from FPGA Fabric through the AHB Interface
59
Figure 27 Smartdesign Connections (Top Level View)
59
Figure 28 MDDR with Single AHB-Lite Interface
60
Table 23 MDDR Throughput (for AHB)
60
Accessing MDDR from the HPDMA
61
Figure 29 MDDR with HPDMA
61
Figure 30 System Builder - Device Features Tab
61
Figure 31 Memory Configurations
62
Figure 32 Clocks Configuration
62
Timing Diagrams
63
Figure 33 AXI Single Write Transaction and Corresponding DDR Controller Commands
63
Figure 34 DDR Controller Command Sequence for Single AXI Write Transaction
63
Figure 35 AXI Single Read Transaction and Corresponding DDR Controller Commands
64
Figure 36 AXI INCR16 Write Transaction and Corresponding DDR Controller Commands
64
Figure 37 AXI INCR16 Write Transaction
65
Figure 38 DDR Controller Command Sequence for AXI INCR16 Write Transaction
65
Figure 39 AXI INCR-16 Read Transaction and Corresponding DDR Controller Commands
65
Timing Optimization Technique for AXI
66
Figure 40 DDR Controller Command Sequence for AXI INCR-16 Read Transaction
66
Table 24 Number of Cycles for AXI/AHB Transactions to MDDR
66
Figure 41 AXI Timing Optimization Logic
67
Figure 42 Timing Diagram
67
DDR Memory Device Examples
69
Example 1: Connecting 32-Bit DDR2 to Mddr_Pads
69
Example 2: Connecting 32-Bit DDR3 to Mddr_Pads with SECDED
70
Figure 43 X16 DDR2 SDRAM Connected to MDDR
70
Example 3: Connecting 16-Bit LPDDR to Mddr_Pads with SECDED
71
Figure 44 ×8 DDR3 SDRAM Connection to MDDR
71
Board Design Considerations
72
MDDR Configuration Registers
72
Figure 45 ×16 LPDDR1 SDRAM Connection to MDDR
72
Table 25 I/O Standards and Calibration Resistance Requirements for MDDR/FDDR
72
SYSREG Configuration Register Summary
73
Table 26 Address Table for Register Interfaces
73
Table 27 SYSREG Configuration Register Summary
73
DDR Controller Configuration Register Summary
74
Table 28 DDR Controller Configuration Register
74
DDR Controller Configuration Register Bit Definitions
78
Table 32 DDRC_DYN_POWERDOWN_CR
79
Table 39 DDRC_INIT_1_CR
84
Table 47 DDRC_DRAM_RD_WR_LATENCY_CR
87
Table 50 DDRC_DRAM_RAS_TIMING_CR
88
Table 52 DDRC_DRAM_T_PD_CR
89
Table 55 DDRC_ODT_PARAM_2_CR
91
Table 57 DDRC_MODE_REG_RD_WR_CR
92
Table 59 DDRC_PWR_SAVE_1_CR
93
Table 61 DDRC_ZQ_LONG_TIME_CR
94
Table 64 DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR
95
Table 66 DDRC_HPR_QUEUE_PARAM_1_CR
97
Table 69 DDRC_LPR_QUEUE_PARAM_2_CR
98
Table 72 DDRC_PERF_PARAM_3_CR
99
Table 74 DDRC_DFI_MIN_CTRLUPD_TIMING_CR
100
Table 77 DDRC_AXI_FABRIC_PRI_ID_CR
101
Table 79 DDRC_SINGLE_ERR_CNT_STATUS_SR
102
Table 81 DDRC_LUE_SYNDROME_1_SR
103
Table 83 DDRC_LUE_SYNDROME_3_SR
104
Table 84 DDRC_LUE_SYNDROME_4_SR
105
Table 86 DDRC_LUE_ADDRESS_1_SR
106
Table 88 DDRC_LCE_SYNDROME_1_SR
107
Table 90 DDRC_LCE_SYNDROME_3_SR
108
Table 91 DDRC_LCE_SYNDROME_4_SR
109
Table 93 DDRC_LCE_ADDRESS_1_SR
110
Table 96 DDRC_LCB_MASK_1_SR
111
Table 98 DDRC_LCB_MASK_3_SR
112
Table 100 DDRC_ECC_INT_SR
113
DDR_FIC Configuration Registers Summary
114
PHY Configuration Register Bit Definitions
114
PHY Configuration Register Summary
114
DDR_FIC Configuration Register Bit Definitions
116
Table 108 DDR_FIC_HPD_SW_RW_EN_CR
117
Table 110 DDR_FIC_SW_WR_ERCLR_CR
118
Table 112 DDR_FIC_NUM_AHB_MASTERS_CR
119
Table 114 DDR_FIC_HPB_ERR_ADDR_2_SR
120
Table 117 DDR_FIC_HPD_SW_WRB_EMPTY_SR
121
Table 119 DDR_FIC_SW_HPD_WERR_SR
122
Appendix A: How to Use the MDDR in Smartfusion2
123
Design Flow Using System Builder
123
Figure 46 System Builder - Device Features Window
124
Figure 47 MSS External DDR Memory Selection
124
Figure 48 I/O Drive Strength Setting
125
Table 124 DDR I/O Standard Configured Based on I/O Drive Strength Setting
125
Figure 49 Selecting I/O Standard as LVCMOS18 or LPDDRI
126
Figure 50 DDR Memory Initialization Settings
128
Figure 51 DDR Memory Timing Settings
129
Figure 52 MSS DDR FIC Subsystem Configuration
130
Figure 53 MDDR Clock Configuration
131
Design Flow Using Smartdesign
132
Figure 54 DDR_FIC Clock Configuration
132
Figure 55 Design Flow
133
Figure 56 MDDR Configurator
133
Figure 57 Memory Interface Configuration
134
Figure 58 MSS External DDR Memory Configurator
134
Figure 59 MDDR Clock Configuration
135
Figure 60 MDDR Clock Configuration
135
Figure 61 FIC_2 Configuration
136
Figure 62 I/O Configuration
136
Use Model 1: Accessing MDDR from FPGA Fabric through the AXI Interface
137
Figure 63 MDDR with AXI Interface
137
Figure 64 MSS External Memory Configuration
138
Figure 65 Configuring FIC_2
138
Figure 66 MDDR Clock Configuration
138
Use Model 2: Accessing MDDR from FPGA Fabric through the AHB Interface
139
Figure 67 Smartdesign Canvas
139
Figure 68 MDDR with Single AHB Interface
140
Use Model 3: Accessing MDDR from Cortex-M3 Processor
141
Figure 69 MDDR with Dual AHB Interface
141
Figure 70 Accessing MDDR from Cortex-M3 Processor
142
Figure 71 MSS External Memory Configuration
142
Use Model 4: Accessing MDDR from the HPDMA
143
Figure 72 Configuring MDDR_CLK
143
Figure 73 Accessing MDDR from HPDMA
144
4 Fabric DDR Subsystem
145
Features
145
Figure 74 System Level FDDR Block Diagram
145
Memory Configurations
146
Performance
146
Table 125 Supported Memory (DDR2, DDR3, and LPDDR1) Configurations
146
Table 126 DDR Speeds
146
I/O Utilization
147
Functional Description
147
Architecture Overview
147
Figure 75 FDDR Subsystem Functional Block Diagram
147
Table 127 I/O Utilization for Smartfusion2 and IGLOO2 Devices
147
Port List
149
Table 128 FDDR Subsystem Interface Signals
149
Table 129 FDDR AXI Slave Interface Signals
151
Table 130 FDDR AHB Slave Interface Signals
154
Initialization
155
Reset Sequence
155
Table 131 FDDR APB Slave Interface Signals
155
ZQ Calibration
156
Figure 76 Reset Sequence
156
Details of Operation
157
Figure 77 DDR_FIC Block Diagram
159
Table 132 FDDR_CLK to FPGA Fabric Clock Ratios
159
Figure 78 AXI Transaction Controller Block Diagram
160
Figure 79 DDR Controller Block Diagram
161
Table 133 SECDED DQ Lines at DDR
162
FDDR Subsystem Features Configuration
163
Memory Type
163
Bus Width Configurations
163
Burst Mode
164
Configuring Dynamic DRAM Constraints
164
Dynamic DRAM Bank Constraints
164
Table 134 Supported Bus Widths
164
Table 135 Supported Burst Modes for M2S150 and M2GL150
164
Table 136 Dynamically Enforced Bank Constraints
165
Table 137 Dynamically Enforced Bank Constraints
165
Table 138 Dynamic DRAM Global Constraints
165
Address Mapping
166
Figure 80 Address Mapping
166
Table 40 DDRC_CKE_RSTN_CYCLES_1_CR
166
Table 41 DDRC_ CKE_RSTN_CYCLES_2_CR
166
Table 34 DDRC_ADDR_MAP_BANK_CR
167
Table 35 DDRC_ADDR_MAP_COL_1_CR
167
Table 36 DDRC_ADDR_MAP_COL_2_CR
167
Table 37 DDRC_ADDR_MAP_ROW_1_CR
167
Table 38 DDRC_ADDR_MAP_ROW_2_CR
167
Table 42 DDRC_INIT_MR_CR
167
Table 43 DDRC_INIT_EMR_CR
167
Table 44 DDRC_INIT_EMR2_CR
167
Table 45 DDRC_INIT_EMR3_CR
167
How to Use FDDR in IGLOO2 Devices
169
Configuring FDDR
169
Figure 81 System Builder - Device Features Window
169
Figure 82 System Builder - Device Features Tab
170
Table 139 Supported Address Width Range for Row, Bank and Column
170
Figure 83 Fabric DDR Memory Configuration
171
Table 140 DDR I/O Standard Is Configured Based on I/O Drive Strength Setting
171
Figure 84 Selecting I/O Standard as LVCMOS18 or LPDDRI
172
Figure 85 Memory Initialization Configuration
174
Figure 86 Memory Timing Configuration
175
Figure 87 System Builder - Peripherals Tab
176
Accessing FDDR from FPGA Fabric through the AXI Interface
177
Figure 88 FDDR Clock Configuration
177
Figure 89 I/O Editor Window
177
Figure 90 FDDR Subsystem with AXI Interface
178
Figure 91 System Builder - Device Features Tab
179
Figure 92 Memory Configuration
179
Figure 93 Fabric DDR Subsystem Configuration Dialog
180
Figure 94 AMBA Master Configuration
180
Figure 95 Clocks Configuration
181
Accessing FDDR from FPGA Fabric through the AHB Interface
182
Figure 96 Smartdesign Connections (Top Level View)
182
Figure 97 FDDR with AHB-Lite Interface
183
Table 141 FDDR Throughput (for AHB)
183
DDR Memory Device Examples
184
Example 1: Connecting 32-Bit DDR2 to Fddr_Pads
184
Example 2: Connecting 32-Bit DDR3 to Fddr_Pads with SECDED
184
Figure 98 X16 DDR2 SDRAM Connected to FDDR
184
Example 3: Connecting 16-Bit LPDDR to Fddr_Pads with SECDED
185
Figure 99 X8 DDR3 SDRAM Connection to FDDR
185
FDDR Configuration Registers
186
Figure 100 X16 LPDDR1 SDRAM Connection to FDDR
186
Table 142 Address Table for Register Interfaces
186
FDDR SYSREG Configuration Register Bit Definitions
187
FDDR SYSREG Configuration Register Summary
187
Table 143 FDDR SYSREG
187
Table 144 PLL_CONFIG_LOW_1
187
Table 145 PLL_CONFIG_LOW_2
188
Table 146 PLL_CONFIG_HIGH
189
Table 147 FDDR_FACC_CLK_EN
189
Table 148 FDDR_FACC_MUX_CONFIG
191
Table 149 FDDR_FACC_DIVISOR_RATIO
191
Table 150 PLL_DELAY_LINE_SEL
192
Table 153 FDDR_INTERRUPT_ENABLE
193
Table 155 PHY_SELF_REF_EN
194
Appendix A: How to Use the FDDR in Smartfusion2 Devices
195
Design Flow Using System Builder
195
Figure 101 System Builder - Device Features Window
196
Figure 102 MSS External DDR Memory Selection
197
Table 161 Supported Address Width Range for Row, Bank and Column Addressing in DDR/LPDDR
197
Table 162 DDR I/O Standard Is Configured Based on I/O Drive Strength Setting
197
Figure 103 Fabric DDR Memory Settings
198
Figure 104 Selecting I/O Standard as LVCMOS18 or LPDDRI
198
Figure 105 DDR Memory Initialization Settings
200
Figure 106 DDR Memory Timing Settings
201
Figure 107 MSS DDR FIC Subsystem Configuration
202
Design Flow Using Smartdesign
203
Figure 108 FDDR Clock Configuration
203
Figure 110 Fabric External Memory DDR Controller Configurator
205
Figure 111 FIC Configuration
206
Figure 112 I/O Configuration
206
Use Model 1: Accessing FDDR from FPGA Fabric through AXI Interface
207
Figure 113 FDDR with AXI Interface
207
Figure 114 FDDR Configuration
208
Figure 115 Fabric CCC Configuration
209
Figure 116 Smartdesign Canvas
209
Use Model 2: Accessing FDDR from FPGA Fabric through AHB Interface
210
Figure 117 Accessing FDDR Subsystem through Dual AHB Interface
210
Figure 118 FIC_2 Configuration
211
Figure 119 MSS CCC Configuration
211
Figure 120 FDDR Configuration
212
Figure 121 Fabric CCC Configuration
213
Figure 122 Coreconfigp IP Configuration
213
Figure 123 Coreconfigp IP Configuration
214
Appendix B: Register Lock Bits Configuration
215
Lock Bit File
215
Lock Bit File Syntax
215
Figure 124 Smartdesign Canvas
215
Locking and Unlocking a Register
216
Figure 125 Lock Bit Configuration File
216
Figure 126 Register Lock Bit Settings Window
216
5 DDR Bridge
218
Figure 127 DDR Bridges in the Smartfusion2/Igloo2 FPGA Device
218
Functional Description
219
Architecture Overview
219
Table 163 Smartfusion2 and IGLOO2 FPGA DDR Bridge Interface
219
Details of Operation
220
Figure 128 DDR Bridge Functional Block Diagram
220
Figure 129 WCB Operation
221
Figure 130 Flow Chart for Read Operation
222
How to Use DDR Bridge in IGLOO2 Device
223
Configuring the DDR Bridge
224
Figure 131 System Builder - Device Features Window
224
High-Speed Data Transactions from HPDMA
225
Figure 132 Configuring HPMS DDR Bridge for HPDMA
225
Figure 133 Configuring HPMS DDR Bridge for Non-Bufferable Region
225
Selecting Non-Bufferable Region
226
SYSREG Control Registers
226
Figure 134 Configuring DDR Bridge
226
Table 164 SYSREG Control Registers
226
DDR Bridge Control Registers in MDDR and FDDR
227
Appendix A: How to Use DDR Bridge in Smartfusion2 Device
227
Table 165 DDR Bridge Control Registers in MDDR and FDDR
227
Figure 135 Configuring MSS DDR Bridge
228
Use Model 1: High Speed Data Transactions from Cortex-M3 Processor
228
Figure 136 Configuring MSS DDR Bridge for Use Model 1
229
Figure 137 Configuring MSS DDR Bridge for Use Model 2
229
Use Model 2: Selecting Non-Bufferable Region
229
6 Soft Memory Controller Fabric Interface Controller
230
Figure 138 System Level SMC_FIC Block Diagram
230
Functional Description
231
Port List
231
Figure 139 SMC_FIC Block Diagram
231
Table 166 SMC_FIC 64-Bit AXI Port List
231
Table 167 SMC_FIC 32-Bit AHB-Lite Port List
235
How to Use SMC_FIC in IGLOO2 Device
236
Figure 140 HPMS External Memory Configurator
236
Figure 141 HPMS SMC_FIC Subsystem Configuration
237
Figure 142 Coresdr_Axi Configuration
237
SYSREG Control Register for SMC_FIC
238
Appendix A: How to Use SMC_FIC in Smartfusion2 Devices
238
Design Flow
238
Figure 109 Design Flow
238
Figure 143 MSS External Memory Configurator
238
Use Model 1: Accessing SDRAM from MSS through Coresdr_Axi
239
Figure 144 Core_Axi Configuration
239
Figure 145 Subsystem Connections in Smartdesign
240
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