Ddr Controller Configuration Register Bit Definitions - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
3.11.3

DDR Controller Configuration Register Bit Definitions

Table 29 • DDRC_DYN_SOFT_RESET_CR
Bit
Number Name
[31:3] Reserved
2 AXIRESET
1 RESET_APB_REG
0 REG_DDRC_SOFT_RSTB
Table 30 • DDRC_DYN_REFRESH_1_CR
Bit
Number Name
[31:15] Reserved
[14:7] REG_DDRC_T_RFC_MIN
6 REG_DDRC_REFRESH_UPDATE_LEVEL 0×0
5 REG_DDRC_SELFREF_EN
[4:0] REG_DDRC_REFRESH_TO_X32
Table 31 • DDRC_DYN_REFRESH_2_CR
Bit
Number Name
Reset
Value
0×0
0×1
0×0
0×0
Reset
Value
0×0
0×23
0×0
0×8
Reset
Value Description
Microsemi Proprietary UG0446 User Guide Revision 7.0
Description
Software should not rely on the value of a reserved
bit. To provide compatibility with future products, the
value of a reserved bit should be preserved across a
read-modify-write operation.
Set when main AXI reset signal is asserted. Reads
and writes to the dynamic registers should not be
carried out. This is a read only bit.
Full soft reset
If this bit is set when the soft reset bit is written as 1,
all APB registers reset to the power-up state.
This is a soft reset.
0: Puts the controller into reset.
1: Takes the controller out of reset.
The controller should be taken out of reset only when
all other registers have been programmed.
Asserting this bit does NOT reset all the APB
configuration registers. Once the soft reset bit is
asserted, the APB register should be modified as
required.
Description
Software should not rely on the value of a reserved
bit. To provide compatibility with future products, the
value of a reserved bit should be preserved across a
read-modify-write operation.
t – Minimum time from refresh to refresh or
RFC(min)
activate (specification: 75 ns to 195 ns).
Unit: clocks.
Toggle this signal to indicate that the refresh
register(s) have been updated.
The value is automatically updated when exiting soft
reset, so it does not need to be toggled initially.
If 1, then the controller puts the DRAM into self
refresh when the transaction store is empty.
Speculative refresh
67