Microchip Technology Microsemi SmartFusion2 User Manual page 148

Fabric DDR Subsystem
The FDDR subsystem has a dedicated clock controller for generating clocks to the components of FDDR
from the base clock (CLK_BASE). The CLK_BASE for the FDDR originates from a fabric CCC or an
external source through the FPGA fabric.
The DDR_FIC facilitates communication between the FPGA fabric masters and AXI transaction
controller. The DDR_FIC can be configured to provide either one 64-bit AXI slave interface or two
independent 32-bit AHB-Lite (AHBL) slave interfaces to the FPGA fabric masters.
The AXI transaction controller receives read and write requests from AXI masters (DDR_FIC) and
schedules for the DDR controller by translating them into DDR controller commands.
The DDR controller receives the commands from the AXI transaction controller. These commands are
queued internally and scheduled for access to the DDR SDRAM while satisfying DDR SDRAM
constraints, transaction priorities, and dependencies between the transactions. The DDR controller in
turn issues commands to the PHY module, which launches and captures data to and from the DDR
SDRAM.
DDR PHY receives commands from the DDR controller and generates DDR memory signals required to
access the external DDR memory.
The 16-bit APB configuration bus provides an interface for configuring the FDDR subsystem registers.
Microsemi ProprietaryUG0446 User Guide Revision 7.0 137