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Fabric DDR Subsystem
Figure 84 • Selecting I/O Standard as LVCMOS18 or LPDDRI
5.
Depending on the application requirement, select the Memory Initialization settings under the
Memory Initialization tab as shown in
•
Select the below performance related settings
•
Burst Length can be selected as 4, 8, or 16. Refer
lengths.
•
Burst order can be selected as sequential or interleaved. Refer
supported burst orders.
•
Timing mode can be selected as 1T or 2T. For more details refer to
page
•
CAS latency is the delay, in clock cycles, between the internal READ command and the
availability of the first bit of output data. Select the CAS latency according to the DDR memory
(Mode register) datasheet.
•
Select the below power saving mode settings. Refer to
for more details.
•
Self-Refresh Enabled
•
Auto Refresh Burst Count
•
Power down Enabled
•
Stop the clock: supported only for LPDDR
•
Deep Power down Enabled: supported only for LPDDR
•
Power down entry time
•
Select the additional performance settings.
•
Additive CAS Latency is defined by EMR[5:3] register of DDR2 memory and by MR1[4:3]
register of DDR3 memory. It enables the DDR2 or DDR3 SDRAM to allow a READ or WRITE
command from DDR Controller after the ACTIVATE command for the same bank prior to tRCD
(MIN). This configuration is part of DDR2 Extended Mode Register and DDR3 Mode Register1.
157.
Microsemi ProprietaryUG0446 User Guide Revision 7.0
Figure 85 on page
163.
Table 135 on page 153
"Power Saving Modes" section on page 151
for supported burst
Table 135 on page 153
for
"1T or 2T Timing" section on
161
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