Ddr Controller Configuration Register Summary; Table 28 Ddr Controller Configuration Register - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
3.11.2

DDR Controller Configuration Register Summary

Table 28 • DDR Controller Configuration Register
Register Name
DDRC_DYN_SOFT_RESET_CR
DDRC_DYN_REFRESH_1_CR
DDRC_DYN_REFRESH_2_CR
DDRC_DYN_POWERDOWN_CR
Reserved
DDRC_MODE_CR
DDRC_ADDR_MAP_BANK_CR
Reserved
DDRC_ADDR_MAP_COL_1_CR
DDRC_ADDR_MAP_COL_2_CR
DDRC_ADDR_MAP_ROW_1_CR
DDRC_ADDR_MAP_ROW_2_CR
DDRC_INIT_1_CR
DDRC_CKE_RSTN_CYCLES_1_CR
DDRC_ CKE_RSTN_CYCLES_2_CR
DDRC_INIT_MR_CR
DDRC_INIT_EMR_CR
DDRC_INIT_EMR2_CR
DDRC_INIT_EMR3_CR
DDRC_DRAM_BANK_TIMING_PARAM_CR
DDRC_DRAM_RD_WR_LATENCY_CR
DDRC_DRAM_RD_WR_PRE_CR
Addres
s Offset
0×000
0×008
0×00C
0×010
0×014
0×018
0×01C
0×020
0×024
0×028
0×02C
0×030
0×034
0×038
0×03C
0×040
0×044
0×048
0×04C
0×050
0×054
0×058
Microsemi Proprietary UG0446 User Guide Revision 7.0
Registe Reset
r Type Source Description
RW/RO PRESET_N DDRC Reset register
RW PRESET_N DDRC Refresh Control
register
RW PRESET_N DDRC Refresh Control
register
RW PRESET_N DDRC Power-Down Control
register
- - -
RW PRESET_N DDRC Mode register
RW PRESET_N DDRC Bank Address Map
register
- - -
RW PRESET_N DDRC Column Address
Map register
RW PRESET_N DDRC Column Address
Map register
RW PRESET_N DDRC Row Address Map
register
RW PRESET_N DDRC Row Address Map
register
RW PRESET_N DDRC Initialization Control
register
RW PRESET_N DDRC Initialization Control
register
RW PRESET_N DDRC Initialization Control
register
RW PRESET_N DDRC MR Initialization
register
RW PRESET_N DDRC EMR Initialization
register
RW PRESET_N DDRC EMR2 Initialization
register
RW PRESET_N DDRC EMR3 Initialization
register
RW PRESET_N DDRC DRAM Bank Timing
Parameter register
RW PRESET_N DDRC DRAM Write Latency
register
RW PRESET_N DDRC DRAM Read-Write
Precharge Timing register
63