Table 136 Dynamically Enforced Bank Constraints; Table 137 Dynamically Enforced Bank Constraints; Table 138 Dynamic Dram Global Constraints - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
Table 136 • Dynamically Enforced Bank Constraints
Row cycle time (t )
RC
Row precharge command
period (t )
RP
Minimum bank active time
(t )
RAS(min)
Maximum bank active time
(t )
RAS(max)
RAS-to-CAS delay (t )
RCD
Write command period (t
WR
Read-to-precharge delay
(t )
RTP
4.6.9.1 Dynamic DRAM Rank Constraints
The timing constraints which affect the transactions to a rank are listed in the following table. The control
bit field must be configured as per the DDR memory vendor specification.
Table 137 • Dynamically Enforced Bank Constraints
Timing Constraints of
DDR Memory
Nominal refresh cycle
time (t or t )
RFC(nom) REFI
Minimum refresh cycle
time t
RFC(min)
RAS-to-RAS delay (t ) REG_DDRC_T_RRD,
RRD
RAS-to-CAS delay (t ) REG_DDRC_T_CCD,
CCD
Four active window (t ) REG_DDRC_T_FAW,
FAW
4.6.9.2 Dynamic DRAM Global Constraints
The timing constraints which affect global transactions are listed in the following table. The control bit
field must be configured as per the DDR memory vendor specification.
Table 138 • Dynamic DRAM Global Constraints
Timing Constraint
Read-to-write turnaround
time
REG_DDRC_T_RC,
Table 46, page 75
REG_DDRC_T_RP,
Table 53, page 78
REG_DDRC_T_RAS_MIN,
Table 50, page 77
REG_DDRC_T_RAS_MAX,
Table 50, page 77
REG_DDRC_T_RCD,
Table 53, page 78
) REG_DDRC_WR2PRE,
Table 48, page 76
REG_DDRC_RD2PRE,
Table 48, page 76
Control Bit
REG_DDRC_T_RFC_NOM_X32,
Table 31, page 67
REG_DDRC_T_RFC_MIN,
Table 30, page 67
Table 53,
page 78
Table 53,
page 78
Table 46,
page 75
Control Bit
REG_DDRC_RD2WR, Table 51,
page 77
Microsemi ProprietaryUG0446 User Guide Revision 7.0
Minimum time between two successive activates to a
given bank.
Minimum time from a precharge command to the next
command affecting that bank.
Minimum time from an activate command to a precharge
command to the same bank.
Maximum time from an activate command to a precharge
command to the same bank.
Minimum time from an activate command to a Read or
Write command to the same bank.
Minimum time from a Write command to a precharge
command to the same bank.
Minimum time from a Read command to a precharge
command to the same bank.
Set this to the current value of additive latency plus half of
the burst length.
Description
Average time between refreshes for a given rank. The
actual time between any two refresh commands may
be larger or smaller than this; this represents the
maximum time allowed between refresh commands
to a given rank when averaged over a large period of
time.
Minimum time from refresh to refresh or activate.
Minimum time between activates from bank A to bank
B.
Minimum time between two reads or two writes (from
bank A to bank B).
Sliding time window in which a maximum of 4 bank
activates are allowed in an 8-bank design. In a
4-bank design, set this register to 0x1.
Description
Minimum time to allow between issuing any Read
command and issuing any WRITE command
154