Table 21 Supported Address Width Range For Row, Bank And Column Addressing In Ddr/Lpddr; Table 22 Ddr I/O Standard Is Configured Based On I/O Drive Strength Setting - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
• For address mapping, the register settings that perform mapping to system address bits for row,
bank and column combinations are automatically computed by the configurator using the address
mapping option. The following table lists the supported range for row, bank, and column.
Table 21 • Supported Address Width Range for Row, Bank and Column Addressing in DDR/LPDDR
Width
Row Address
Bank Address
Column Address
For more information refer to the
• Select the I/O Drive Strength as Half Drive Strength or Full Drive Strength, as shown in
Figure 13,
setting.
Table 22 • DDR I/O Standard is Configured Based on I/O Drive Strength Setting
I/O Drive Strength
Half Drive Strength
Full Drive Strength
DDR2
12–16
2–3
9–12
"Address Mapping" section.
page 36. The following table lists how the DDR I/O standard is configured based on this
Memory Type
DDR2
SSTL18I
SSTL18II
Microsemi Proprietary UG0446 User Guide Revision 7.0
DDR3 LPDDR
12–16 12–16
2–3 2–3
9–12 9–12
DDR3
SSTL15I
SSTL15II
35