Microchip Technology Microsemi SmartFusion2 User Manual page 24

MDDR Subsystem
Table 6 • AXI Slave Interface Signals (continued)
Signal Name
MDDR_DDR_AXI_S_ARVALID
MDDR_DDR_AXI_S_AWADDR[31:0]
MDDR_DDR_AXI_S_AWBURST[1:0]
MDDR_DDR_AXI_S_AWID[3:0]
MDDR_DDR_AXI_S_AWLEN[3:0]
MDDR_DDR_AXI_S_AWLOCK[1:0]
Direction Polarity
Input
Input
Input
Input
Input
Input
Microsemi Proprietary UG0446 User Guide Revision 7.0
Description
High Indicates the validity of read address
and control information.
1: Address and control information valid
0: Address and control information not
valid
Indicates write address. The write
address bus gives the address of the
first transfer in a write burst transaction.
Note: DDR_FIC AXI interface
supports only 64-bit
aligned addresses
Indicates burst type. The burst type,
coupled with the size information,
details how the address for each
transfer within the burst is calculated.
00: FIXED - Fixed-address burst FIFO-
type (Not Supported)
01: INCR - Incrementing-address burst
normal sequential memory
10: WRAP - Incrementing-address
burst that wraps to a lower address at
the wrap boundary
11: Reserved
Indicates identification tag for the write
address group of signals.
Indicates burst length. The burst length
gives the exact number of transfers in a
burst. This information determines the
number of data transfers associated
with the address.
0000: 1
0001: 2
0010: 3
0011: 4
0100: 5
0101: 6
0110: 7
0111: 8
1000: 9
1001: 10
1010: 11
1011: 12
1100: 13
1101: 14
1110: 15
1111: 16
Indicates lock type. This signal provides
additional information about the atomic
characteristics of the write transfer.
00: Normal access
01: Exclusive access
10: Locked access
11: Reserved
.
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