Figure 123 Coreconfigp Ip Configuration - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
Figure 123 • CoreConfigP IP Configuration
11. Instantiate user AHB master logic in the SmartDesign canvas to access the FDDR through the AHB
interface. The AHB master clock frequency should be the same as the FDDR DDR_FIC clock
frequency.
12. Connect the AHB master to the FDDR AHB slave0 interface through CoreAHBLite. Connect the
FIC_0 master to the FDDR AHB slave1 interface through CoreAHBLite.
13. Make the other connections in the SmartDesign canvas, as shown in the following illustration.
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