Phy Configuration Register Summary; Phy Configuration Register Bit Definitions; Ddr_Fic Configuration Registers Summary - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
3.11.4

PHY Configuration Register Summary

Table 102 • PHY Configuration Register Summary
Register Name
Reserved
PHY_DATA_SLICE_IN_USE_CR
Reserved
3.11.5

PHY Configuration Register Bit Definitions

Table 103 • PHY_DATA_SLICE_IN_USE_CR
Bit
Number Name
[31:5] Reserved
[4:0] REG_PHY_DATA_SLICE_IN_USE
3.11.6

DDR_FIC Configuration Registers Summary

Table 104 • DDR_FIC Configuration Register Summary
Register Name
DDR_FIC_NB_ADDR_CR
DDR_FIC_NBRWB_SIZE_CR
DDR_FIC_BUF_TIMER_CR
DDR_FIC_HPD_SW_RW_EN_CR
DDR_FIC_HPD_SW_RW_INVAL_CR
DDR_FIC_SW_WR_ERCLR_CR
DDR_FIC_ERR_INT_ENABLE
Offset
0×200 to 0×22C
0×230
0×234 to 0×3C8
Reset
Value
0×0
0×0
Addres
s Offset R/W
0×400 RW
0×404 RW
0×408 RW
0×40C RW
0×410 RW
0×414 RW
0×418 RW
Microsemi Proprietary UG0446 User Guide Revision 7.0
Reset
Type Source Description
- - -
RW PRESET_N PHY data slice in use register
- - -
Description
Software should not rely on the value of a reserved bit.
To provide compatibility with future products, the value
of a reserved bit should be preserved across a read-
modify-write operation.
Data bus width selection for read FIFO RE generation.
One bit for each data slice.
1: Data slice is valid.
0: Read data responses are ignored.
Note: The PHY data slice 0 must always be
enabled.
Reset
Source Description
PRESET_ Indicates the base address of the non-
N bufferable address region.
PRESET_ Indicates the size of the non-bufferable
N address region.
PRESET_ 10-bit timer interface used to configure the
N timeout register.
PRESET_ Enable write buffer and read buffer register
N for AHBL master1 and master2.
PRESET_ Invalidates write buffer and read buffer for
N AHBL master1 and master2.
PRESET_ Clear bit for error status by AHBL master1
N and master2 write buffer.
PRESET_ Used for Interrupt generation.
N
103