Page 1 UG0446 User Guide SmartFusion2 and IGLOO2 FPGA High Speed DDR Interfaces...
Page 2 About Microsemi ©2019 Microsemi, a wholly owned Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of subsidiary of Microchip Technology Inc. All semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets.
Page 3: Table Of Contents
Contents 1 Revision History ........... . . 1 Revision 7.0 .
Page 4 3.12.4 Use Model 2: Accessing MDDR from FPGA Fabric Through the AHB Interface ..128 3.12.5 Use Model 3: Accessing MDDR from Cortex-M3 Processor ......130 3.12.6 Use Model 4: Accessing MDDR from the HPDMA .
Page 5 5.5.2 Use Model 2: Selecting Non-Bufferable Region ........218 6 Soft Memory Controller Fabric Interface Controller .
Page 6 Figures Figure 1 System Level MDDR Block Diagram ..........6 Figure 2 MDDR Subsystem Functional Block Diagram .
Page 7 Figure 55 Design Flow ..............122 Figure 56 MDDR Configurator .
Page 8 Figure 114 FDDR Configuration ............197 Figure 115 Fabric CCC Configuration .
Page 9 Tables Table 1 Additional Documents ............3 Table 2 Supported Memory (DDR2, DDR3 and LPDDR1) Configurations .
Page 10 Table 55 DDRC_ODT_PARAM_2_CR ........... . . 80 Table 56 DDRC_ADDR_MAP_COL_3_CR .
Page 11 Table 114 DDR_FIC_HPB_ERR_ADDR_2_SR ..........109 Table 115 DDR_FIC_SW_ERR_ADDR_1_SR .
Page 12: Revision History
Revision History Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. Revision 7.0 The following is a summary of the changes in this revision. •...
Page 13: Revision 1.0
Revision History • Restructured the user guide (SARs 47314, 45974, 45616, 43424, 46149, 46446). • Updated MDDR Subsystem, page 5 (SARs 55041, 58032, 51465, 58034, 58035, 58037, 51933, 58038, 57034, and 57207). • Updated Fabric DDR Subsystem, page 134 (SARs 58034, 58035, 58037, 51933, 58038, 57034, 57207, and 58038).
Page 14: Overview
Overview Overview ® This user guide describes the high speed memory interfaces in SmartFusion 2 System-on-Chip (SoC) ® field programmable gate array (FPGA) and IGLOO 2 FPGA devices. The high speed interfaces microcontroller/memory subsystem double-data rate (MDDR) subsystem and fabric DDR (FDDR) subsystem provide access to DDR memories for high-speed data transfers.
Page 15 Overview Table 1 • Additional Documents (continued) Document Description UG0447: IGLOO2 and SmartFusion2 High Speed SmartFusion2 and IGLOO2 devices integrate hard high-speed Serial Interfaces User Guide serial interfaces (PCIe, XAUI/XGXS, SERDES). This document describes the SmartFusion2 and IGLOO2SmartFusion2 and IGLOO2 high-speed serial interfaces. UG0449: SmartFusion2 and IGLOO2 Clocking SmartFusion2 and IGLOO2 clocking resources include on-chip Resources User Guide...
Page 16: Mddr Subsystem
MDDR Subsystem MDDR Subsystem The MDDR is a hardened ASIC block for interfacing the DDR2, DDR3, and LPDDR1 memories. The MDDR subsystem is used to access DDR memories for high-speed data transfers and code execution., and includes a DDR memory controller, DDR PHY, and arbitration logic to support multiple masters. DDR memory connected to the MDDR subsystem can be accessed by the MSS/HPMS masters and master logic implemented in the FPGA fabric (FPGA fabric master).
Page 17: Memory Configurations
MDDR Subsystem Figure 1 • System Level MDDR Block Diagram MSS/HPMS Cortex-M3 Microcontroller SDRAM MSS/HPMS Cache Transaction 64-Bit AXI Controller Controller Controller Bridge APB Config. DDR_FIC Register AHB Bus Matrix MDDR HPDMA APB_2 FIC_0 FIC_1 16-Bit APB 64-Bit AXI / Single 32-Bit AHBL / Dual 32-Bit AHBL AXI/AHB...
Page 18: Performance
MDDR Subsystem • Data line MDDR_DQ_ECC[0] when data width is x8 Table 2 • Supported Memory (DDR2, DDR3 and LPDDR1) Configurations SmartFusion2 and IGLOO2 Devices Width M2S/M2GL 005/010/025/060/090 M2S/M2GL 050 Memory SECDED M2S/M2GL150- (FCS325, M2S/M2GL 050 Depth Width Mode) FCV484 VF400, FG484) (FG896) M2S/M2GL150(FC1152)
Page 19: Functional Description
MDDR Subsystem Table 4 • I/O Utilization for SmartFusion2 and IGLOO2 Devices 16-bit Bank0 (53 pins) Bank0 (53 pins) Bank0 (53 pins) Bank2 (53 pins) 9-bit Bank0 (47 pins) – – Bank2 (47 pins) 8-bit Bank0 (41 pins) – – Bank2 (41 pins) Note: If MDDR is configured for LPDDR, one more IO also available for every 8-bit as the LPDDR does not have DQS_N.
Page 20: Port List
MDDR Subsystem 3.5.2 Port List Table 5 • MDDR Subsystem Interface Signals Signal Name Type Polarity Description APB_S_PCLK – APB clock. This clock drives all the registers of the APB interface. APB_S_PRESET_N APB reset signal. This is an active low signal. This drives the APB interface and is used to generate the soft reset for the DDR controller as well.
Page 21 MDDR Subsystem Table 5 • MDDR Subsystem Interface Signals (continued) Signal Name Type Polarity Description MDDR_ADDR[15:0] – Dram address bits MDDR_BA[2:0] – Dram bank address MDDR_DM_RDQS[3:0] In/out – DRAM data mask – from bidirectional pads MDDR_DQS[3:0] In/out – DRAM single-ended data strobe output – for bidirectional pads MDDR_DQS_N[3:0] In/out...
Page 22: Table 6 Axi Slave Interface Signals
MDDR Subsystem 3.5.2.1 AXI Slave Interface The following table describes the MDDR AXI slave interface signals. These signals will be available only if the MDDR interface is configured for AXI mode. For more AXI protocol details, refer to AMBA AXI v1.0 protocol specification.
Page 23 MDDR Subsystem Table 6 • AXI Slave Interface Signals (continued) Signal Name Direction Polarity Description MDDR_DDR_MDDR_DDR_AXI_S_ARADDR[31:0] Input Indicates initial address of a read burst transaction. Note: DDR_FIC AXI interface supports only 64-bit aligned addresses. MDDR_DDR_AXI_S_ARBURST[1:0] Input Indicates burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
Page 24 MDDR Subsystem Table 6 • AXI Slave Interface Signals (continued) Signal Name Direction Polarity Description MDDR_DDR_AXI_S_ARVALID Input High Indicates the validity of read address and control information. 1: Address and control information valid 0: Address and control information not valid MDDR_DDR_AXI_S_AWADDR[31:0] Input Indicates write address.
Page 25: Table 7 Ahb Slave Interface Signals
MDDR Subsystem Table 6 • AXI Slave Interface Signals (continued) Signal Name Direction Polarity Description MDDR_DDR_AXI_S_AWSIZE[1:0] Input Indicates the maximum number of data bytes to transfer in each data transfer, within a burst. 00 to 10 : Not Supported 11: 8 MDDR_DDR_AXI_S_AWVALID Input High...
Page 26: Table 8 Mddr Apb Slave Interface Signals
MDDR Subsystem Table 7 • AHB Slave Interface Signals (continued) Signal Name Direction Polarity Description MDDR_DDR_AHBx_S_HADDR[31:0] Input Indicates AHB address initiated by Fabric master. MDDR_DDR_AHBx_S_HBURST[2:0] Input Indicates AHB burst type from Fabric master. 000: Single burst 001: Incrementing burst of undefined length 010: 4-beat wrapping burst 011: 4-beat incrementing burst 100: 8-beat wrapping burst...
Page 27: Initialization
MDDR Subsystem Table 8 • MDDR APB Slave Interface Signals (continued) Signal Name Direction Polarity Description MDDR_APB_S_PWRITE Input High Indicates APB write control signal form Fabric master MDDR_APB_S_PADDR[10:2] Input Indicates APB address initiated by Fabric master. MDDR_APB_S_PWDATA[15:0] Input Indicates APB write data from Fabric master. 3.5.3 Initialization After power-up, the MDDR needs to have all of the configuration registers written to establish the...
Page 28: Figure 3 Reset Sequence
MDDR Subsystem Figure 3 • Reset Sequence PO_RESET_N 50 MHz Clock Enable Enable I/Os DDRIO Calibration SC_HPMS_RESET_N (for IGLOO2) SC_MSS_RESET_N (for SmartFusion2) MPLL Lock MDDR_AXI_RESET_N 3.5.3.3 ZQ Calibration This is applicable for DDR3 only. The ZQ calibration command is used to calibrate DRAM output drivers ) and on-die termination (ODT) values.
Page 29: Details Of Operation
MDDR Subsystem 3.5.3.4.2 Read Leveling MDDR does not perform dynamic Read DQS Gate Training and Data Eye Training. Instead, these functions are achieved by using built-in static delay values automatically generated by Libero SoC for the MDDR automatic register initialization. 3.5.3.4.3 Read Gate The DQS gate is aligned by the Libero SoC auto-generated MDDR initialization code containing fixed...
Page 30: Table 9 Mddr_Clk To Fpga Fabric Clock Ratios
MDDR Subsystem • Dual AHB-32 bit interfaces If the AXI-64 interface is selected, the DDR_FIC acts as an AXI to AXI synchronous bridge. In this mode, DDR_FIC provides FPGA fabric masters to access the MDDR subsystem through locked transactions. For this purpose, a user configurable 20-bit down counter keeps track of the duration of the locked transfer.
Page 31: Figure 5 Axi Transaction Controller Block Diagram
MDDR Subsystem Figure 5 • AXI Transaction Controller Block Diagram AXI Transaction Controller AXI Slave Transaction 64-Bit AXI Bus Interface 0 Handler from MSS/HPMS DDR Bridge Controller Priority Block AXI Slave 64-Bit AXI Bus Re-Order Buffer Interface 1 from DDR_FIC The AXI transaction controller comprises four major blocks: •...
Page 32: Figure 6 Ddr Controller Block Diagram
MDDR Subsystem Table 10 • Priority Level Configuration Writes from DSG bus Writes from HPDMA/AHB bus Writes from Fabric master having the ID as PRIORITY_ID IGLOO2 PRIORITY_ENABLE_BIT=01/10/11 (Type-1/2/3) Reads from HPDMA/AHB bus Reads from Fabric master having the ID as PRIORITY_ID Writes from HPDMA/AHB bus Writes from Fabric master having the ID as PRIORITY_ID...
Page 33 MDDR Subsystem 3.5.4.3.1 Address Mapping Read and write requests to the DDR controller requires a system address. The controller is responsible for mapping this system address with rank, bank, row, and column address to DRAM. The address mapper maps linear request addresses to DDR memory addresses by selecting the source bit that maps to each and every applicable DDR memory address bit.
Page 34: Figure 7 Ddr Rmw Operation (32-Bit Ddr Bus Width And Burst Length 8)
MDDR Subsystem Figure 7 • DDR RMW Operation (32-Bit DDR Bus Width and Burst Length 8) The following illustration shows the DDR controller burst transactions to DRAM for unaligned 64-bit AXI write transaction. The DDR controller is configured for DDR3 memory, 16-bit bust width, and burst length Figure 8 •...
Page 35: Table 11 Secded Dq Lines At Ddr
MDDR Subsystem The SECDED bits are interlaced with the data bits, as listed in the following table. Table 11 • SECDED DQ Lines at DDR SECDED Data Pins M2S/M2GL005/010/025 M2S/M2GL 050 /060/090 (FCS325, VF400, M2S/M2GL 050 M2S/M2GL 150 Mode M2S/M2GL150-FCV484 FG484) (FG896) (FC1152)
Page 36: Mddr Subsystem Features Configuration
MDDR Subsystem • The DDR controller keeps the DDR memory devices in Self-refresh mode whenever the self refresh is enabled and the REG_DDRC_SELFREF_EN register bit is set and no reads or writes are pending in the controller. • The controller takes the DDR memory out of Self-refresh mode whenever the REG_DDRC_SELFREF_EN input is deasserted or new commands are received by the controller.
Page 37: Table 13 Supported Burst Modes
MDDR Subsystem Supported burst modes for DDR SDRAM types and PHY widths are listed in the following table. For M2GL050 devices, only sequential burst mode and a burst length of 8 are supported. Table 13 • Supported Burst Modes Sequential/Interleaving Bus Width Memory Type LPDDR1...
Page 38: Table 15 Dynamically-Enforced Bank Constraints
MDDR Subsystem 3.5.5.5.1 Dynamic DRAM Rank Constraints The timing constraints that affect the transactions to a rank are listed in the following table. The control bit field must be configured as per the DDR memory vendor specification. Table 15 • Dynamically-Enforced Bank Constraints Timing Constraints of DDR Memory...
Page 39: Figure 10 Address Mapping
MDDR Subsystem [Internal base] + [register value] = [source address bit number] EQ 1 For example, reading the description for REG_DDRC_ADDRMAP_COLB3, the internal base is 3; so when the full data bus is in use, the column bit 4 is determined by 3+ [register value]. If this register is programmed to 2, then the source address bit is: 3+2 = 5.
Page 40 MDDR Subsystem 3.5.5.6.1 Example In this example, the Address map registers are configured to access a 512 MB DDR3 SDRAM memory (MT41J512M8RA) from the MDDR subsystem as shown in "Example 2: Connecting 32-Bit DDR3 to MDDR_PADs with SECDED" section on page 59.
Page 41: Table 29 Ddrc_Dyn_Soft_Reset_Cr
MDDR Subsystem The DDR controller has a transaction store, shared for low and high priority transactions. The DDRC_PERF_PARAM_1_CR register can be configured for allocating the transaction store between the low and high priority transactions. For example, if the REG_DDRC_LPR_NUM_ENTRIES field is configured to 0, the controller allocates more time to high priority transactions.
Page 42: Table 17 Ddr Memory Regions
MDDR Subsystem of DDR that is, the accessible DDR memory from AHB bus matrix is 0x00000000-0x4FFFFFFF which is 1 GB. Table 17 • DDR Memory Regions DDR Memory Region DDR Memory Space 0×00000000-0×0FFFFFFF 0×10000000-0×1FFFFFFF 0×20000000-0×2FFFFFFF 0×30000000-0×3FFFFFFF 0×40000000-0×4FFFFFFF 0×50000000-0×5FFFFFFF 0×60000000-0×6FFFFFFF 0×70000000-0×7FFFFFFF 0×80000000-0×8FFFFFFF 0×90000000-0×9FFFFFFF 0×A0000000-0×AFFFFFFF...
Page 43: How To Use Mddr In Igloo2 Device
MDDR Subsystem If 2 GB of DDR memory is connected to MDDR, only 8 regions are available (0-7). The following table shows the DDR regions available for address mode settings. Table 19 • Accessed DDR Memory Regions Based on Mode Settings for a 2 GB Memory DDR Memory Regions Visible at MSS/HPMS DDR Address Space for Different Modes MSS/HPMS DDR MSS/HPMS DDR...
Page 44: Configuring Mddr
MDDR Subsystem Figure 11 • System Builder—Device Features Window For more information about how to use MDDR in the SmartFusion2 devices, refer to "Appendix A: How to Use the MDDR in SmartFusion2" section on page 112. 3.6.1 Configuring MDDR The following steps configure the MDDR: Microsemi Proprietary UG0446 User Guide Revision 7.0...
Page 45: Figure 12 Mdr Initialization Path
MDDR Subsystem Check the HPMS External DDR Memory (MDDR) check box under the Device Features tab and leave the other check boxes unchecked. The following image shows the System Builder - Device Features tab. Figure 12 • MDR Initialization Path Selecting the MDDR under HPMS External Memory check box in the System Builder performs the following actions: •...
Page 46: Table 21 Supported Address Width Range For Row, Bank And Column Addressing In Ddr/Lpddr
MDDR Subsystem • For address mapping, the register settings that perform mapping to system address bits for row, bank and column combinations are automatically computed by the configurator using the address mapping option. The following table lists the supported range for row, bank, and column. Table 21 •...
Page 47: Figure 13 I/O Drive Strength Setting
MDDR Subsystem Figure 13 • I/O Drive Strength Setting For only LPDDR memory, the I/O standard and I/O calibration settings are available as shown in the following illustration. • Select I/O standard as LVCMOS18 or LPDDRI. For the Microsemi M2GL_EVAL_KIT board, select LPDDRI(SSTL18) because the board is designed to use the LPDDRI I/O standard.
Page 48: Figure 14 Selecting I/O Standard As Lvcmos18 Or Lpddri
MDDR Subsystem Figure 14 • Selecting I/O Standard as LVCMOS18 or LPDDRI Depending on the application requirement, select the Memory Initialization settings under the Memory Initialization tab as shown in Figure 15 on page • Select the following performance-related settings: •...
Page 49 MDDR Subsystem command from DDR Controller after the ACTIVATE command for the same bank prior to tRCD (MIN). This configuration is part of DDR2 Extended Mode register and DDR3 mode register1. • CAS Write Latency (CWL) is defined by DDR3 MR2[5:3] and is the delay in clock cycles from the releasing of the internal write to the latching of the first data in.
Page 50: Figure 15 Memory Initialization Configuration
MDDR Subsystem Figure 15 • Memory Initialization Configuration Select the memory timing settings under the Memory Timing tab according to the DDR memory vendor datasheet, as shown in the following image. For more details, refer to "Configuring Dynamic DRAM Constraints" section on page Microsemi Proprietary UG0446 User Guide Revision 7.0...
Page 51: Figure 16 Memory Timing Configuration
MDDR Subsystem Figure 16 • Memory Timing Configuration The configurator also provides the option to import and export the register configurations. The configuration settings are stored in eNVM. Configuration files for accessing LPDDR memory on IGLOO2 evaluation kit can be downloaded from: www.microsemi.com/soc/documents/LPDDR_Emcraft_Config.zip.
Page 52: Figure 17 System Builder - Peripherals Tab
MDDR Subsystem • Deep PowerDown enabled: No • No Activity clocks for Entry: 320 • Memory Timing • Time To Hold Reset Before INIT: 67584 clks • MRD: 4 clks • RAS (Min): 8 clks • RAS (Max): 8192 clks •...
Page 53: Figure 18 Mddr_Clk Configuration
MDDR Subsystem The MDDR_CLK must be selected as multiples of 1, 2, 3, 4, 6, or 8 of HPMS_CLK. This clock can be configured using the HPMS_CCC configurator. The maximum frequency of MDDR_CLK is 333.33 MHz. The following illustration shows the MDDR_CLK configuration. Figure 18 •...
Page 54: Accessing Mddr From Fpga Fabric Through The Axi Interface
MDDR Subsystem Figure 20 • I/O Editor Window 3.6.2 Accessing MDDR from FPGA Fabric through the AXI Interface The AXI master in the FPGA fabric accesses the DDR memory through the MDDR subsystem. The following illustration shows the MDDR subsystem with the AXI interface. The MDDR registers are configured from the FPGA fabric using the CoreConfigMaster IP through the CoreConfigP IP APB interface.
Page 55: Figure 21 Mddr With Axi Interfaces
MDDR Subsystem Figure 21 • MDDR with AXI Interfaces HPMS MDDR HPMS DDR HPDMA Bridge Transaction Controller eNVM Controller SDRAM DDR_FIC AHB Bus Matrix APB Config FIC_0 FIC_1 APB_2 CoreConfigP CoreConfigMaster Master Slave 1 Slave n Fabric IGLOO2 Read, write, and read-modify-write transactions are initiated by the AXI master to read from or write the data to the DDR memory after initializing the MDDR registers.
Page 56: Figure 22 System Builder - Device Features Tab
MDDR Subsystem Go to the System Builder - Device Features tab, check the HPMS External DDR Memory check box, and select MDDR. Leave the rest of the check boxes unchecked. The following illustration shows the System Builder - Device Features tab. Figure 22 •...
Page 57: Figure 24 Peripherals Tab With The Master Added And Configure Icon Highlighted
MDDR Subsystem Figure 24 • Peripherals Tab with the Master Added and Configure Icon Highlighted In the Configuring AMBA_MASTER_0 dialog, select the Interface Type as AXI and then click OK. The following image shows the AMBA Master - Configuration dialog. Figure 25 •...
Page 58: Figure 26 System Clocks Configuration
MDDR Subsystem Figure 26 • System Clocks Configuration 10. Navigate to the Memory Map tab giving the required data in the rest of the System Builder tabs. 11. Instantiate your AXI master logic in the SmartDesign canvas to access the MDDR subsystem through the AXI interface.
Page 59: Accessing Mddr From Fpga Fabric Through The Ahb Interface
MDDR Subsystem Figure 27 • SmartDesign Connections (Top Level View) For MDDR AXI throughput, see AC422: SmartFusion2 - Optimizing DDR Controller for Improved Efficiency - Libero v11.7 Application Note. 3.6.3 Accessing MDDR from FPGA Fabric Through the AHB Interface The MDDR subsystem can be used to access the DDR memory using the AHB-Lite interface. The following illustration shows the MDDR with AHB-Lite interface.
Page 60: Figure 28 Mddr With Single Ahb-Lite Interface
MDDR Subsystem Figure 28 • MDDR with Single AHB-Lite Interface HPMS MDDR HPMS DDR HPDMA Bridge Transaction Controller eNVM Controller SDRAM DDR_FIC AHB Bus Matrix APB Config FIC_0 FIC_1 APB_2 CoreConfigP CoreConfigMaster Master AHB_Lite Slave 1 Slave n Fabric IGLOO2 The procedure for accessing the MDDR from AHB master in the FPGA fabric is the same as in "Accessing MDDR from FPGA Fabric through the AXI Interface"...
Page 61: Accessing Mddr From The Hpdma
MDDR Subsystem 3.6.4 Accessing MDDR from the HPDMA The HPDMA controller can access DDR SDRAM connected to the MDDR subsystem through the HPMS DDR bridge. The following illustration shows the MDDR with HPDMA. Figure 29 • MDDR with HPDMA HPMS MDDR HPMS DDR HPDMA...
Page 62: Figure 31 Memory Configurations
MDDR Subsystem Figure 31 • Memory Configurations Configure the System Clock and Subsystem clocks in the Clocks tab. The following image shows the Clocks configuration dialog. • Select the On-chip 25/50 MHz RC Oscillator • Configure HPMS_CCC for MDDR_CLK Configure HPMS_CLK, APB_0_CLK, FIC_0_CLK clocks as 111 MHz and the MDDR_CLK clock as 333 MHz.
Page 63: Timing Diagrams
MDDR Subsystem Timing Diagrams This section shows the operation of the DDR controller with AXI interface with Timing diagrams. The DDR3 16-bit micron memory model is used to perform the read and write transactions from MDDR Fabric Interface (DDR_FIC). The AXI/AHB clock is configured for 166 MHz and MDDR clock is configured for 332 MHz, that is, FIC clock to MDDR clock ratio is 1:2.
Page 64: Figure 35 Axi Single Read Transaction And Corresponding Ddr Controller Commands
MDDR Subsystem Figure 35 • AXI Single Read Transaction and Corresponding DDR Controller Commands MDDR_CLK_N MDDR_CS_N MDDR_ODT MDDR_RAS_N MDDR_RESET_N MDDR_WE_N 0000 MDDR_ADDR MDDR_BA MDDR_DM_RDQS MDDR_DQS MDDR_DQS_N Read transac on to DDR MDDR_DQ Memory ini ated by MDDR MDDR_DQS_TMATCH_0_IN MDDR_DQS_TMATCH_0_OUT DDR read controls ARID 00000000 ARADDR...
Page 65: Figure 37 Axi Incr16 Write Transaction
MDDR Subsystem Figure 37 • AXI INCR16 Write Transaction DDR write controls AWID AWADDR AWLEN AWSIZE AWLOCK AWBURST AWVALID AWREADY WSTRB WLAST WVALID 13 14 WDATA WREADY RESP BVALID BREADY 10 11 12 14 15 16 18 19 20 22 23 24 26 27 28 30 31 32 Figure 38 •...
Page 66: Timing Optimization Technique For Axi
MDDR Subsystem Figure 40 • DDR Controller Command Sequence for AXI INCR-16 Read Transaction MDDR_CAS_N MDDR_CKE MDDR_CLK MDDR_CLK_N MDDR_CS_N MDDR_ODT MDDR_RAS_N MDDR_RESET_N MDDR_WE_N 0000 0008 0010 0018 0020 0028 0030 0038 MDDR_ADDR MDDR_BA MDDR_DM_RDQS Read transac on to MDDR_DQS DDR Memory ini ated MDDR_DQS_N MDDR_DQ MDDR_DQS_TMATCH_0_IN...
Page 67: Figure 41 Axi Timing Optimization Logic
MDDR Subsystem Figure 41 • AXI Timing Optimization Logic System Builder Generated Component Other AXI signals AWREADY AWVALID WREADY Fabric AXI MDDR/FDDR Master DDR_FIC WVALID ARREADY ARVALID FCCC DDR_FIC_SUBSYSTEM_CLK AXI RESET The AXI data lines into the DDR_FIC can now be relaxed with additional half AXI clock cycle as the AXI valid signals are delayed by half AXI clock cycle.
Page 68 MDDR Subsystem */INST_FDDR_IP:F_ARADDR* \ */INST_FDDR_IP:F_ARBURST* \ */INST_FDDR_IP:F_ARID* \ */INST_FDDR_IP:F_ARLEN*\ */INST_FDDR_IP:F_ARLOCK* \ */INST_FDDR_IP:F_ARSIZE* \ */INST_FDDR_IP:F_AWADDR* \ */INST_FDDR_IP:F_AWBURST* \ */INST_FDDR_IP:F_AWID* \ */INST_FDDR_IP:F_AWLEN* \ */INST_FDDR_IP:F_AWLOCK* \ */INST_FDDR_IP:F_AWSIZE* \ */INST_FDDR_IP:F_WDATA* \ */INST_FDDR_IP:F_WID* \ */INST_FDDR_IP:F_WLAST \ */INST_FDDR_IP:F_WSTRB* \ */INST_FDDR_IP:F_BREADY* \ */INST_FDDR_IP:F_RMW_AXI \ */INST_FDDR_IP:F_RREADY* \ /* The following constraints provide a relaxation constraint on the signals of 1 clock period. */ set delay2 [ expr 2000/$ddr_clock_frequency ] set_max_delay $delay2 -to [ get_pins { \ */INST_FDDR_IP:F_ARVALID* \...
Page 69: Ddr Memory Device Examples
MDDR Subsystem */INST_MSS_*_IP:F_ARSIZE* \ */INST_MSS_*_IP:F_AWADDR* \ */INST_MSS_*_IP:F_AWBURST* \ */INST_MSS_*_IP:F_AWID* \ */INST_MSS_*_IP:F_AWLEN* \ */INST_MSS_*_IP:F_AWLOCK* \ */INST_MSS_*_IP:F_AWSIZE* \ */INST_MSS_*_IP:F_WDATA* \ */INST_MSS_*_IP:F_WID* \ */INST_MSS_*_IP:F_WLAST \ */INST_MSS_*_IP:F_WSTRB* \ */INST_MSS_*_IP:F_BREADY \ */INST_MSS_*_IP:F_RMW_AXI \ */INST_MSS_*_IP:F_RREADY \ /* The following constraints provide a relaxation constraint on the signals of 1 clock period. */ set delay2 [ expr 2000/$ddr_clock_frequency ] set_max_delay $delay2 -to [ get_pins { \ */INST_MSS_*_IP:F_ARVALID* \...
Page 70: Example 2: Connecting 32-Bit Ddr3 To Mddr_Pads With Secded
MDDR Subsystem Figure 43 • x16 DDR2 SDRAM Connected to MDDR MDDR_PADS MT47H64M16 MDDR_CAS_N CASN MDDR_CKE MDDR_CLK CLK_P MDDR_CLK_N CLK_N MDDR_CS_N MDDR_ODT MDDR_IMP_CALIB MDDR_RAS_N RASN MDDR_WE_N MDDR_ADDR[12:0] ADDR[12:0] MDDR_BA[2:0] BA[2:0] MDDR_DM_RDQS[1:0] MDDR_DQS[1:0] UDQS, LDQS MDDR_DQS_N[1:0] UDQS#, LDQS# MDDR_DQ[15:0] DQ[15:0] MDDR_DM_RDQS[3:2] MDDR_DQS[3:2] MDDR_DQS_N[3:2] MT47H64M16...
Page 71: Example 3: Connecting 16-Bit Lpddr To Mddr_Pads With Secded
MDDR Subsystem Figure 44 • ×8 DDR3 SDRAM Connection to MDDR MDDR_PADS CASN MDDR_CAS_N MDDR_CKE CLK_P MDDR_CLK CLK_N MDDR_CLK_N MDDR_CS_N MDDR_ODT RASN MDDR_RAS_N MDDR_IMP_CALIB MDDR_RESET_N RSTN MDDR_WE_N MDDR_ADDR[15:0] ADDR[15:0] MDDR_BA[2:0] BA[2:0] MDDR_DM_RDQS[0] MDDR_DQS[0] MDDR_DQS_N[0] DQS# MDDR_DQ[7:0] DQ[7:0] MT41J512M8RA MDDR_DM_RDQS[1] MDDR_DQS[1] MDDR_DQS_N[1] DQS# MDDR_DQ[15:8]...
Page 72: Board Design Considerations
MDDR Subsystem Figure 45 • ×16 LPDDR1 SDRAM Connection to MDDR MDDR_PADS MT46H32M16LF MDDR_CAS_N CASN MDDR_CKE MDDR_CLK CLK_P MDDR_CLK_N CLK_N MDDR_IMP_CALIB MDDR_CS_N MDDR_RAS_N RASN MDDR_WE_N MDDR_ADDR[12:0] ADDR[12:0] MDDR_BA[1:0] BA[2:0] MDDR_DM_RDQS[1:0] UDM, LDM MDDR_DQS[0] LDQS MDDR_DQS[1] UDQS MDDR_DQ[15:0] DQ[15:0] MDDR_DM_RDQS_ECC MDDR_DQS_ECC MT46H32M16LF MDDR_DQ_ECC[1:0] MDDR_DQS_TMATCH_0_IN...
Page 73: Sysreg Configuration Register Summary
MDDR Subsystem The following table lists the categories of registers and their offset addresses. The base address of the MDDR subsystem registers is 0x40020800. Table 26 • Address Table for Register Interfaces Registers Address Offset Space DDR Controller Configuration Register 0×000:0×1FC Reserved 0×200:0×3FC...
Page 74: Ddr Controller Configuration Register Summary
MDDR Subsystem 3.11.2 DDR Controller Configuration Register Summary Table 28 • DDR Controller Configuration Register Addres Registe Reset Register Name s Offset r Type Source Description DDRC_DYN_SOFT_RESET_CR 0×000 RW/RO PRESET_N DDRC Reset register DDRC_DYN_REFRESH_1_CR 0×008 PRESET_N DDRC Refresh Control register DDRC_DYN_REFRESH_2_CR 0×00C PRESET_N DDRC Refresh Control...
Page 75 MDDR Subsystem Table 28 • DDR Controller Configuration Register (continued) Addres Registe Reset Register Name s Offset r Type Source Description DDRC_DRAM_MR_TIMING_PARAM_CR 0×05C PRESET_N DDRC DRAM Mode Register Timing Parameter register DDRC_DRAM_RAS_TIMING_CR 0×060 PRESET_N DDRC DRAM RAS Timing Parameter register DDRC_DRAM_RD_WR_TRNARND_TIME_CR 0×064 PRESET_N DDRC DRAM Read Write...
Page 76 MDDR Subsystem Table 28 • DDR Controller Configuration Register (continued) Addres Registe Reset Register Name s Offset r Type Source Description DDRC_WR_QUEUE_PARAM_CR 0×0B0 PRESET_N DDRC Performance Parameter register DDRC_PERF_PARAM_2_CR 0×0B4 PRESET_N DDRC Performance Parameter register DDRC_PERF_PARAM_3_CR 0×0B8 PRESET_N DDRC Performance Parameter register DDRC_DFI_RDDATA_EN_CR 0×0BC...
Page 77 MDDR Subsystem Table 28 • DDR Controller Configuration Register (continued) Addres Registe Reset Register Name s Offset r Type Source Description DDRC_LCE_SYNDROME_2_SR 0×110 PRESET_N DDRC last corrected error syndrome register DDRC_LCE_SYNDROME_3_SR 0×114 PRESET_N DDRC last corrected error syndrome register DDRC_LCE_SYNDROME_4_SR 0×118 PRESET_N DDRC last corrected error syndrome register...
Page 78: Ddr Controller Configuration Register Bit Definitions
MDDR Subsystem 3.11.3 DDR Controller Configuration Register Bit Definitions Table 29 • DDRC_DYN_SOFT_RESET_CR Reset Number Name Value Description [31:3] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 79: Table 32 Ddrc_Dyn_Powerdown_Cr
MDDR Subsystem Table 31 • DDRC_DYN_REFRESH_2_CR [31:15] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read- modify-write operation. [14:3] REG_DDRC_T_RFC_NOM_X32 0×52...
Page 80 MDDR Subsystem Table 33 • DDRC_MODE_CR REG_DDRC_MOBILE 0×0 1: Mobile/LPDDR1 DRAM device in use 0: Non-mobile DRAM device in use REG_DDRC_SDRAM 0×0 1: SDRAM mode 0: Non-SDRAM mode. Only present in designs that support SDRAM and/or mSDR devices. REG_DDRC_TEST_MODE 0×0 1: Controller is in test mode 0: Controller is in normal mode [4:2]...
Page 81 MDDR Subsystem Table 35 • DDRC_ADDR_MAP_COL_1_CR Reset Number Name Value Description [31:16] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 82 MDDR Subsystem Table 36 • DDRC_ADDR_MAP_COL_2_CR [15:12] REG_DDRC_ADDRMAP_COL_B8 0×0 Full bus width mode: Selects column address bit 9. Half bus width mode: Selects column address bit 11. Quarter bus width mode: Selects column address bit 12. Valid range: 0 to 7, and 15 Internal base: 8 The selected address bit is determined by adding the internal base to the value of this field.
Page 83 MDDR Subsystem Table 37 • DDRC_ADDR_MAP_ROW_1_CR [15:12] REG_DDRC_ADDRMAP_ROW_B0 0×0 Selects the address bits used as row address bit 0. Valid range: 0 to 11 Internal base: 6 The selected address bit for each of the row address bits is determined by adding the internal base to the value of this field.
Page 84: Table 39 Ddrc_Init_1_Cr
MDDR Subsystem Table 38 • DDRC_ADDR_MAP_ROW_2_CR [3:0] REG_DDRC_ADDRMAP_ROW_B15 0×0 Selects the address bit used as row address bit 15. Valid range: 0 to 11, and 15 Internal base: 21 The selected address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.
Page 85 MDDR Subsystem Table 40 • DDRC_CKE_RSTN_CYCLES_1_CR [15:8] REG_DDRC_PRE_CKE_X1024 0×0 The 10-bit REG_DDRC_PRE_CKE_X1024 [9:0] value is spit across the two registers: DDRC_CKE_RSTN_CYCLES_1_CR and DDRC_CKE_RSTN_CYCLES_2_CR. [7:0] bits of REG_DDRC_PRE_CKE_X1024. Cycles to wait after reset before driving CKE High to start the DRAM initialization sequence. Units: 1,024 clock cycles.
Page 86 MDDR Subsystem Table 42 • DDRC_INIT_MR_CR [15:0] REG_DDRC_MR 0×095A Value to be loaded into the DRAM Mode register. Bit 8 is for the DLL and the setting here is ignored. The controller sets appropriately. During DRAM initialization procedure, the controller will send the mode register setting to DRAM. The mode register sets the DRAM burst length, burst type, CAS latency (CL), and operating mode.
Page 87: Table 47 Ddrc_Dram_Rd_Wr_Latency_Cr
MDDR Subsystem Table 46 • DDRC_DRAM_BANK_TIMING_PARAM_CR [11:6] REG_DDRC_T_RC 0×0 : Minimum time between activates to same bank (specification: 65 ns for DDR2-400 and smaller for faster parts). Unit: clocks. [5:0] REG_DDRC_T_FAW 0×0 : Valid only in burst-of-8 mode. At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks Table 47 •...
Page 88: Table 50 Ddrc_Dram_Ras_Timing_Cr
MDDR Subsystem Table 49 • DDRC_DRAM_MR_TIMING_PARAM_CR [31:13] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. [12:3] REG_DDRC_T_MOD 0×0 Present for DDR3 only (replaces REG_DDRC_T_MRD functionality...
Page 89: Table 52 Ddrc_Dram_T_Pd_Cr
MDDR Subsystem Table 51 • DDRC_DRAM_RD_WR_TRNARND_TIME_CR [4:0] REG_DDRC_WR2RD 0×0 WL + tWTR + BL/2 Minimum time from WRITE command to READ command. Includes time for bus turnaround and recovery times and all per-bank, per- rank, and global constraints. Unit: clocks. where, WL: Write latency.
Page 90 MDDR Subsystem Table 54 • DDRC_ODT_PARAM_1_CR (continued) Reset Number Name Value Description [11:8] REG_DDRC_RD_ODT_DELAY 0×0 The delay, in clock cycles, from issuing a READ command to setting ODT values associated with that command. Recommended value for DDR2 is CL – 4. [7:4] REG_DDRC_WR_ODT_DELAY 0×0 The delay, in clock cycles, from issuing a WRITE command to...
Page 91: Table 55 Ddrc_Odt_Param_2_Cr
MDDR Subsystem 3.11.3.1 DDRC_ODT_PARAM_2_CR Table 55 • DDRC_ODT_PARAM_2_CR Reset Number Name Value Description [31:10] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 92: Table 57 Ddrc_Mode_Reg_Rd_Wr_Cr
MDDR Subsystem Table 56 • DDRC_ADDR_MAP_COL_3_CR (continued) Numbe Reset Name Value Description REG_DDRC_DIS_ACT_BYPASS 0×0 Only present in designs supporting activate bypass. When 1, disable bypass path for high priority read activates REG_DDRC_DIS_RD_BYPASS 0×0 Only present in designs supporting read bypass. When 1, disable bypass path for high priority read page hits.
Page 93: Table 59 Ddrc_Pwr_Save_1_Cr
MDDR Subsystem Table 58 • DDRC_MODE_REG_DATA_CR [31:16] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. [15:0] REG_DDRC_MR_DATA 0×0 Mode register write data...
Page 94: Table 61 Ddrc_Zq_Long_Time_Cr
MDDR Subsystem Table 61 • DDRC_ZQ_LONG_TIME_CR Reset Number Name Value Description [31:10] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 95: Table 64 Ddrc_Zq_Short_Int_Refresh_Margin_2_Cr
MDDR Subsystem Table 63 • DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR (continued) [3:0] REG_DDRC_REFRESH_MARGIN 0×02 Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. Microsemi recommends using the default value. Unit: Multiples of 32 clocks.
Page 96 MDDR Subsystem Table 65 • DDRC_PERF_PARAM_1_CR (continued) Rese Valu Number Name Description [15:13] REG_DDRC_BURST_RDWR 0×0 001: Burst length of 4 010: Burst length of 8 100: Burst length of 16 All other values are reserved. This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM.
Page 97: Table 66 Ddrc_Hpr_Queue_Param_1_Cr
MDDR Subsystem Table 66 • DDRC_HPR_QUEUE_PARAM_1_CR Reset Number Name Value Description [31:16] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 98: Table 69 Ddrc_Lpr_Queue_Param_2_Cr
MDDR Subsystem Table 68 • DDRC_LPR_QUEUE_PARAM_1_CR (continued) Reset Number Name Value Description [3:0] REG_DDRC_LPR_XACT_RUN_LENGTH 0×0 Number of transactions that are serviced once the LPR queue goes critical is the smaller of this value and number of transactions available. Units: Transactions. Table 69 •...
Page 99: Table 72 Ddrc_Perf_Param_3_Cr
MDDR Subsystem Table 71 • DDRC_PERF_PARAM_2_CR REG_DDRC_BURST_MODE 0×0 1: Interleaved burst mode 0: Sequential burst mode The burst mode programmed in the DRAM mode register and the order of the input data to the controller should both match the value programmed in the REG_DDRC_BURST_MODE register.
Page 100: Table 74 Ddrc_Dfi_Min_Ctrlupd_Timing_Cr
MDDR Subsystem Table 74 • DDRC_DFI_MIN_CTRLUPD_TIMING_CR Reset Number Name Value Description [31:10] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. [9:0] REG_DDRC_DFI_T_CTRLUP_MIN 0×03...
Page 101: Table 77 Ddrc_Axi_Fabric_Pri_Id_Cr
MDDR Subsystem Table 76 • DDRC_DYN_SOFT_RESET_ALIAS_CR (continued) Reset Number Name Value Description RESET_APB_REG 0×0 Full soft reset If this bit is set when the soft reset bit is written as ‘1’, all APB registers reset to the power-up state. REG_DDRC_SOFT_RSTB 0×0 This is a soft reset.
Page 102: Table 79 Ddrc_Single_Err_Cnt_Status_Sr
MDDR Subsystem Table 78 • DDRC_SR [5:3] DDRC_CORE_REG_OPERATING_MODE 0×0 Operating mode. This is 3 bits wide in designs with mobile support and 2-bits in all other designs. Non-mobile designs: 000: Init 001: Normal 010: Power-down 011: Self Refresh Mobile designs: 000: Init 001: Normal 010: Power-down...
Page 103: Table 81 Ddrc_Lue_Syndrome_1_Sr
MDDR Subsystem Table 80 • DDRC_DOUBLE_ERR_CNT_STATUS_SR [31:6] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Table 81 • DDRC_LUE_SYNDROME_1_SR Reset Number Name...
Page 104: Table 83 Ddrc_Lue_Syndrome_3_Sr
MDDR Subsystem Table 82 • DDRC_LUE_SYNDROME_2_SR DDRC_REG_ECC_SYNDROMES 0×0 72 bits are split into five registers. [15:0] [31:16] bits of DDRC_REG_ECC_SYNDROMES. First data which has SECDED error in it. 72 bits consists of the following: SECDED: [71:64] – SECDED [63:00] – Data In the same clock cycle, if one lane has a correctable error and the other lane has an uncorrectable error, the syndrome for the uncorrectable error is sent on this bus.
Page 105: Table 84 Ddrc_Lue_Syndrome_4_Sr
MDDR Subsystem Table 84 • DDRC_LUE_SYNDROME_4_SR Reset Number Name Value Description [31:16] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 106: Table 86 Ddrc_Lue_Address_1_Sr
MDDR Subsystem Table 85 • DDRC_LUE_SYNDROME_5_SR [7:0] DDRC_REG_ECC_SYNDROMES 0×0 72 bits are split into five registers. [71:64] bits of DDRC_REG_ECC_SYNDROMES. First data which has SECDED error in it. 72 bits consists of the following: SECDED: [71:64] – SECDED [63:00] – Data In the same clock cycle, if one lane has a correctable error and the other lane has an uncorrectable error, the syndrome for the uncorrectable error is sent on this bus.
Page 107: Table 88 Ddrc_Lce_Syndrome_1_Sr
MDDR Subsystem Table 88 • DDRC_LCE_SYNDROME_1_SR Reset Number Name Value Description [31:16] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 108: Table 90 Ddrc_Lce_Syndrome_3_Sr
MDDR Subsystem Table 89 • DDRC_LCE_SYNDROME_2_SR [15:0] DDRC_REG_ECC_SYNDROMES 0×0 72 bits are split into five registers. [31:16] bits of DDRC_REG_ECC_SYNDROMES. First data which has SECDED error in it. 72 bits consists of the following: SECDED: [71:64] – SECDED [63:00] – Data In the same clock cycle, if one lane has a correctable error and the other lane has an uncorrectable error, the syndrome for the uncorrectable error is sent on this bus.
Page 109: Table 91 Ddrc_Lce_Syndrome_4_Sr
MDDR Subsystem Table 91 • DDRC_LCE_SYNDROME_4_SR Reset Number Name Value Description [31:16] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 110: Table 93 Ddrc_Lce_Address_1_Sr
MDDR Subsystem Table 92 • DDRC_LCE_SYNDROME_5_SR [7:0] DDRC_REG_ECC_SYNDROMES 0×0 72 bits are split into five registers. [71:64] bits of DDRC_REG_ECC_SYNDROMES. First data which has SECDED error in it. 72 bits consists of the following SECDED: [71:64] – SECDED [63:00] – Data In the same clock cycle, if one lane has a correctable error and the other lane has an uncorrectable error, the syndrome for the uncorrectable error is sent on this bus.
Page 111: Table 96 Ddrc_Lcb_Mask_1_Sr
MDDR Subsystem Table 95 • DDRC_LCB_NUMBER_SR [31:7] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. [6:0] DDRC_LCB_BIT_NUM 0×0 Indicates the location of the bit that caused a single-bit error in...
Page 112: Table 98 Ddrc_Lcb_Mask_3_Sr
MDDR Subsystem Table 97 • DDRC_LCB_MASK_2_SR [15:0] DDRC_LCB_MASK 0×0 64 bits are split into four registers. [31:16] bits of DDRC_LCB_MASK. Indicates the mask of the corrected data. 1: On any bit indicates that the bit has been corrected by the DRAM SECDED logic.
Page 113: Table 100 Ddrc_Ecc_Int_Sr
MDDR Subsystem Table 99 • DDRC_LCB_MASK_4_SR [15:0] DDRC_LCB_MASK 0×0 64 bits are split into four registers. [63:48] bits of DDRC_LCB_MASK. Indicates the mask of the corrected data. 1: On any bit indicates that the bit has been corrected by the DRAM SECDED logic.
Page 114: Phy Configuration Register Summary
MDDR Subsystem 3.11.4 PHY Configuration Register Summary Table 102 • PHY Configuration Register Summary Reset Register Name Offset Type Source Description Reserved 0×200 to 0×22C PHY_DATA_SLICE_IN_USE_CR 0×230 PRESET_N PHY data slice in use register Reserved 0×234 to 0×3C8 3.11.5 PHY Configuration Register Bit Definitions Table 103 •...
Page 115 MDDR Subsystem Table 104 • DDR_FIC Configuration Register Summary (continued) Addres Reset Register Name s Offset R/W Source Description DDR_FIC_NUM_AHB_MASTERS_CR 0×41C PRESET_ Defines whether one or two AHBL 32-bit masters are implemented in fabric. DDR_FIC_HPB_ERR_ADDR_1_SR 0×420 PRESET_ Tag of write buffer for which error response is received is placed in this register.
Page 116: Ddr_Fic Configuration Register Bit Definitions
MDDR Subsystem 3.11.7 DDR_FIC Configuration Register Bit Definitions Table 105 • DDR_FIC_NB_ADDR_CR Reset Number Name Value Description [31:16] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 117: Table 108 Ddr_Fic_Hpd_Sw_Rw_En_Cr
MDDR Subsystem Table 107 • DDR_FIC_BUF_TIMER_CR [31:10] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. [9:0] DDR_FIC_TIMER 0×0 10-bit timer interface used to configure timeout register.
Page 118: Table 110 Ddr_Fic_Sw_Wr_Erclr_Cr
MDDR Subsystem Table 109 • DDR_FIC_HPD_SW_RW_INVAL_CR (continued) Reset Number Name Value Description Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. DDR_FIC_flshM2 0×0 1: Flush write buffer for AHBL master2.
Page 119: Table 112 Ddr_Fic_Num_Ahb_Masters_Cr
MDDR Subsystem Table 111 • DDR_FIC_ERR_INT_ENABLE SYR_SW_WR_ERR 0×0 Status bit. Goes High when error response is received for bufferable write request. Goes Low when processor serves interrupt and makes clear bit for AHBL master1. SYR_HPD_WR_ERR 0×0 Status bit. Goes High when error response is received for bufferable write request.
Page 120: Table 114 Ddr_Fic_Hpb_Err_Addr_2_Sr
MDDR Subsystem Table 114 • DDR_FIC_HPB_ERR_ADDR_2_SR Reset Number Name Value Description [31:16] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. [15:0] DDR_FIC_M1_ERR_ADD 0×0...
Page 121: Table 117 Ddr_Fic_Hpd_Sw_Wrb_Empty_Sr
MDDR Subsystem Table 117 • DDR_FIC_HPD_SW_WRB_EMPTY_SR Reset Number Name Value Description [31:7] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. DDR_FIC_M1_RBEMPTY 0×0 1: Read buffer of AHBL master1 does not have valid data.
Page 122: Table 119 Ddr_Fic_Sw_Hpd_Werr_Sr
MDDR Subsystem Table 119 • DDR_FIC_SW_HPD_WERR_SR Reset Bit Number Name Value Description [31:9] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 123: Appendix A: How To Use The Mddr In Smartfusion2
MDDR Subsystem Table 121 • DDR_FIC_LOCK_TIMEOUTVAL_2_CR [3:0] CFGR_LOCK_TIMEOUT_REG 0×0 20 bits are split into two registers. [19:16] bits of CFGR_LOCK_TIMEOUT_REG Lock timeout 20-bit register. Indicates maximum number of cycles a master can hold the bus for locked transfer. If master holds the bus for locked transfer more than the required cycles, an interrupt is generated.
Page 124: Figure 46 System Builder - Device Features Window
MDDR Subsystem Figure 46 • System Builder - Device Features Window The following steps describe how to configure the MDDR. Check the MSS External Memory check box under the Device Features tab, select MDDR and leave the other check boxes unchecked. The following image shows the System Builder - Device Features tab.
Page 125: Figure 48 I/O Drive Strength Setting
MDDR Subsystem Navigate to the Memories tab. Depending on the application requirement, select the memory settings under the General tab, as shown in the following image. • Memory Type can be selected as DDR2, DDR3, or LPDDR. • The Data width can be selected as 32-bit, 16-bit, or 8-bit. Refer to Table 12 on page 25 supported data widths for various SmartFusion2 device packages.
Page 126: Figure 49 Selecting I/O Standard As Lvcmos18 Or Lpddri
MDDR Subsystem For only LPDDR memory, the I/O standard and I/O calibration settings are available as shown in the following image. • Select I/O standard as LVCMOS18 or LPDDRI. For Microsemi M2S_EVAL_KIT board select LPDDRI(SSTL18) as the board is designed to use LPDDRI I/O standard. Note: If LVCMOS18 is selected, all IOs are configured to LVCMOS1.8 except CLK/CLK_N.CLK and CLK_N are configured to LPDDRI standard because they are differential signals.
Page 127 MDDR Subsystem • Power down entry time • Select the additional performance settings for DDR3 memory. • Additive CAS Latency is defined by EMR[5:3] register of DDR2 memory and by MR1[4:3] register of DDR3 memory. It enables the DDR2 or DDR3 SDRAM to allow a READ or WRITE command from DDR Controller after the ACTIVATE command for the same bank prior to tRCD (MIN).
Page 128: Figure 50 Ddr Memory Initialization Settings
MDDR Subsystem Figure 50 • DDR Memory initialization Settings Select the Memory Timing settings under the Memory Timing tab according to the DDR memory vendor datasheet as shown in the following illustration. For more details, refer to "Configuring Dynamic DRAM Constraints" section on page Microsemi Proprietary UG0446 User Guide Revision 7.0...
Page 129: Figure 51 Ddr Memory Timing Settings
MDDR Subsystem Figure 51 • DDR Memory Timing Settings The configurator also provides the option to import and export the register configurations. Configuration files for accessing DDR3 memory on SmartFusion2 Development kit can be downloaded from www.microsemi.com/soc/documents/MDDR3_16Bit_SB.zip. Configuration files for accessing LPDDR memory on SmartFusion2 Starter kit can be downloaded from www.microsemi.com/soc/documents/LPDDR_Emcraft_Config.zip.
Page 130: Figure 52 Mss Ddr Fic Subsystem Configuration
MDDR Subsystem • No Activity clocks for Entry: 320 Memory Timing • Time To Hold Reset Before INIT - 67584 clks • MRD: 4 clks • RAS (Min): 8 clks • RAS (Max): 8192 clks • RCD: 6 clks • RP: 7 clks •...
Page 131: Figure 53 Mddr Clock Configuration
MDDR Subsystem Figure 53 • MDDR Clock Configuration DDR_FIC_CLK drives the DDR_FIC slave interface and defines the frequency at which the FPGA fabric subsystem connected to this interface is intended to run. DDR_FIC_CLK can be configured as a ratio of MDDR_CLK (1, 2, 3, 4, 6, 8, 12, or 16) using the Clocks configurator.
Page 132: Design Flow Using Smartdesign
MDDR Subsystem Figure 54 • DDR_FIC Clock Configuration 3.12.2 Design Flow Using SmartDesign The following flow chart illustrates the design flow for using the MDDR subsystem to access external DDR memory. The design flow consists of two parts: • Libero SoC flow – This includes configuring the type of DDR memory, choosing fabric master interface type, clocking, and DDR I/O settings.
Page 133: Figure 55 Design Flow
MDDR Subsystem Figure 55 • Design Flow The following sections explain the configuration steps in the flow chart. 3.12.2.1 MSS External Memory Configuration The MDDR subsystem is configured through the MDDR configurator, which is part of the MSS configurator in the Libero SoC design software. The following image shows the MDDR configurator. Figure 56 •...
Page 134: Figure 57 Memory Interface Configuration
MDDR Subsystem Double click the MDDR Configurator, which gives the following choices for the external memory interface type as shown in the following image. • Double Data Rate: This option must be selected to access the external DDR memories (DDR2, DDR3 and LPDDR).
Page 135: Figure 59 Mddr Clock Configuration
MDDR Subsystem Figure 59 • MDDR Clock Configuration DDR_SMC_FIC_CLK drives the DDR_FIC slave interface and defines the frequency at which the FPGA fabric subsystem connected to this interface is intended to run. DDR_SMC_FIC_CLK can be configured as a ratio of MDDR_CLK (1, 2, 3, 4, 6, 8, 12, or 16) through the MSS_CCC configurator in Libero SoC, as shown in the following image.
Page 136: Figure 61 Fic_2 Configuration
MDDR Subsystem Figure 61 • FIC_2 Configuration When enabling this option, the MDDR_APB_S_PCLK and FIC_2_APB_M_PCLK signals are exposed in SmartDesign. MDDR_APB_S_PCLK must be connected to FIC_2_APB_M_PCLK. The FIC_2_APB_M_PCLK clock is generated from the MSS_CCC and is identical to M3_CLK/4. 3.12.2.3 I/O Configuration I/O settings such as like ODT and drive strength can be configured as shown in the following image using the I/O Editor in the Libero design software.
Page 137: Use Model 1: Accessing Mddr From Fpga Fabric Through The Axi Interface
MDDR Subsystem 3.12.3 Use Model 1: Accessing MDDR from FPGA Fabric Through the AXI Interface The MDDR subsystem can be used to access DDR memory as shown in the following illustration. This use model follows the steps "Design flow using SmartDesign" for using MDDR. The AXI master in the FPGA fabric accesses the DDR memory through the MDDR subsystem.
Page 138: Figure 64 Mss External Memory Configuration
MDDR Subsystem Figure 64 • MSS External Memory Configuration Configure FIC_2, as shown in the following image, to enable the MDDR subsystem APB interface for configuring the MDDR registers using APB master in the FPGA fabric. Figure 65 • Configuring FIC_2 Configure the MSS_CCC for MDDR_CLK and DDR_SMC_FIC_CLK.
Page 139: Use Model 2: Accessing Mddr From Fpga Fabric Through The Ahb Interface
MDDR Subsystem Make the other connections in the SmartDesign canvas, as shown in the following illustration. Figure 67 • SmartDesign Canvas 10. To verify the design in Libero SoC software, create a SmartDesign testbench project and instantiate a DDR memory model provided by the DDR memory vendor. Simulate the design and observe the AXI read and write transactions.
Page 140: Figure 68 Mddr With Single Ahb Interface
MDDR Subsystem Figure 68 • MDDR with Single AHB Interface MDDR MSS DDR Bridge Transaction Masters SDRAM Controller Controller DDR_FIC Master AHB-Lite Slave 1 Slave n FPGA Fabric To use a dual rather than single AHB interface to the MDDR, set the CFG_NUM_AHB_MASTERS bit in "DDR_FIC_NUM_AHB_MASTERS_CR"...
Page 141: Use Model 3: Accessing Mddr From Cortex-M3 Processor
MDDR Subsystem Figure 69 • MDDR with Dual AHB Interface MDDR MSS DDR Bridge Transaction Masters SDRAM Controller Controller DDR_FIC Master Master AHB-Lite AHB-Lite Slave 1 Slave 1 Slave n Slave n FPGA Fabric The steps for accessing the MDDR from one or two AHB masters in the FPGA fabric is the same as in "Use Model 1: Accessing MDDR from FPGA Fabric Through the AXI Interface"...
Page 142: Figure 70 Accessing Mddr From Cortex-M3 Processor
MDDR Subsystem Figure 70 • Accessing MDDR from Cortex-M3 Processor Go to the System Builder - Device Features tab and check the MSS External Memory check box and leave the rest of the check boxes unchecked. Figure 16 on page 40 shows the System Builder - Device Features tab.
Page 143: Use Model 4: Accessing Mddr From The Hpdma
MDDR Subsystem Figure 72 • Configuring MDDR_CLK Navigate to the Memory Map tab giving the required data in the rest of the System Builder tabs. Click Finish, the system builder creates the design and generates. Connect the clock resources to the MSS component in the SmartDesign canvas. To verify the design in Libero SoC software, create the SmartDesign testbench project and instantiate a DDR memory model provided by the DDR memory vendor.
Page 144: Figure 73 Accessing Mddr From Hpdma
MDDR Subsystem Figure 73 • Accessing MDDR from HPDMA The steps for accessing the MDDR from the HPDMA are the same as in "Use Model 3: Accessing MDDR from Cortex-M3 Processor" section on page 130. Use the generated firmware project to access DDR memory from the HPDMA through the MDDR.
Page 145: Fabric Ddr Subsystem
Fabric DDR Subsystem Fabric DDR Subsystem The FDDR is a hardened ASIC block for interfacing the DDR2, DDR3, and LPDDR1 memories. The FDDR subsystem is used to access DDR memories for high-speed data transfers. The FDDR subsystem includes the DDR memory controller, DDR PHY, and arbitration logic to support multiple masters. FPGA fabric masters communicate with the DDR memories interfaced to the FDDR subsystem through AXI or AHB interfaces.
Page 146: Memory Configurations
Fabric DDR Subsystem The FDDR subsystem accepts data transfer requests from AXI or AHB interfaces. Any read or write transactions to the DDR memories can occur through the AXI or AHBL masters in the FPGA fabric through DDR_FIC interface. Note: The maximum DDR3 data rate supported by FDDR is 333MHz/667Mbps. Therefore, Write Leveling is not mandatory and the interface works if the board layout includes length matching and follows AC393 SmartFusion2 and IGLOO2 Board Design Guidelines Application...
Page 147: I/O Utilization
Fabric DDR Subsystem I/O Utilization The following table shows the I/O utilization for SmartFusion2 and IGLOO2 devices corresponding to supported bus widths. The remaining I/Os in bank 0 can be used for general purposes. Table 127 • I/O Utilization for SmartFusion2 and IGLOO2 Devices FDDR Bus Width M2S050/M2GL050 (FG896) M2S150/M2GL150 (FC1152)
Page 148 Fabric DDR Subsystem The FDDR subsystem has a dedicated clock controller for generating clocks to the components of FDDR from the base clock (CLK_BASE). The CLK_BASE for the FDDR originates from a fabric CCC or an external source through the FPGA fabric. The DDR_FIC facilitates communication between the FPGA fabric masters and AXI transaction controller.
Page 149: Port List
Fabric DDR Subsystem 4.5.2 Port List Table 128 • FDDR Subsystem Interface Signals Signal Name Type Polarity Description APB_S_PCLK – APB clock. This clock drives all the registers of the APB interface. APB_S_PRESET_N APB reset signal. This is an active low signal. This drives the APB interface and is used to generate the soft reset for the DDR controller as well.
Page 150 Fabric DDR Subsystem Table 128 • FDDR Subsystem Interface Signals (continued) Signal Name Type Polarity Description APB_SLAVE – APB slave interface 3.0 bus DRAM Interface FDDR_CAS_N DRAM CASN FDDR_CKE High DRAM CKE FDDR_CLK – DRAM single-ended clock – for differential pads FDDR_CLK_N –...
Page 151: Table 129 Fddr Axi Slave Interface Signals
Fabric DDR Subsystem Table 128 • FDDR Subsystem Interface Signals (continued) Signal Name Type Polarity Description FDDR_DQS_TMATCH_0_OUT High DQS enables output for timing match between DQS and system clock. For simulations, tie to FDDR_DQS_TMATCH_0_IN. FDDR_DQS_TMATCH_1_OUT High DQS enables output for timing match between DQS and system clock.
Page 152 Fabric DDR Subsystem Table 129 • FDDR AXI Slave Interface Signals (continued) Signal Name Direction Polarity Description AXI_S_RDATA[63:0] Output Indicates read data. AXI_S_RID[3:0] Output Read ID tag. This signal is the ID tag of the read data group of signals. AXI_S_RLAST Output High...
Page 153 Fabric DDR Subsystem Table 129 • FDDR AXI Slave Interface Signals (continued) Signal Name Direction Polarity Description AXI_S_ARSIZE[1:0] Input Indicates the maximum number of data bytes to transfer in each data transfer, within a burst. 00: 1 01: 2 10: 4 11: 8 AXI_S_ARVALID Input...
Page 154: Table 130 Fddr Ahb Slave Interface Signals
Fabric DDR Subsystem Table 129 • FDDR AXI Slave Interface Signals (continued) Signal Name Direction Polarity Description AXI_S_AWVALID Input High Indicates whether valid write address and control information are available. 1: Address and control information available 0: Address and control information not available AXI_S_BREADY Input High...
Page 155: Initialization
Fabric DDR Subsystem Table 130 • FDDR AHB Slave Interface Signals (continued) Signal Name Direction Polarity Description AHBx_S_HTRANS[1:0] Input Indicates AHB transfer type from Fabric master. 00: IDLE 01: BUSY 10: NONSEQUENTIAL 11: SEQUENTIAL AHBx_S_HMASTLOCK Input High Indicates AHB master lock signal from Fabric master. AHBx_S_HWRITE Input High...
Page 156: Zq Calibration
Fabric DDR Subsystem 4.6.1.1 DDRIO Calibration Each DDRIO has an ODT feature, which is calibrated depending on the DDR I/O standard. DDR I/O calibration occurs after the DDR I/Os are enabled. If the impedance feature is enabled, impedance can be programmed to the desired value in three ways: •...
Page 157: Details Of Operation
Fabric DDR Subsystem Other activities are not performed by the controller for the duration of t and t . All DRAM banks ZQinit ZQCS are precharged and t met before ZQCL or ZQCS commands are issued by the DDR controller. 4.6.2.1 DRAM Training High Speed DDR3 memories typically requires the DDR controller to implement Write-Leveling, Read...
Page 158 Fabric DDR Subsystem base clock (FDDR_SUBSYSTEM_CLK) for the FDDR comes from a fabric CCC or an external source through the FPGA fabric. The FDDR clock controller is associated with a dedicated PLL (FPLL) for clock synthesis and de-skewing the internal DDR_FIC clock from the base clock. The FDDR clock controller consists of an FPLL and fabric alignment clock controller (FACC).
Page 159: Figure 77 Ddr_Fic Block Diagram
Fabric DDR Subsystem In the event of loss of FPLL lock, even though its output is not exactly in phase lock with the reference, the FPLL still generates a clock. User logic in the FPGA fabric can use the FPLL_LOCK signal to prevent communication with the FDDR subsystem during this time.
Page 160: Figure 78 Axi Transaction Controller Block Diagram
Fabric DDR Subsystem Table 132 • FDDR_CLK to FPGA Fabric Clock Ratios (continued) DIVISOR_A[1:0] DDR_FIC DIVISOR[2:0] FDDR_CLK: FPGA FABRIC Clock Ratio 12:1 4.6.3.3 AXI Transaction Controller The AXI transaction controller receives 64-bit AXI transactions from DDR_FIC and translates them into DDR controller transactions.
Page 161: Figure 79 Ddr Controller Block Diagram
Fabric DDR Subsystem 4.6.3.3.4 Reorder Buffer The reorder buffer receives data from the DDR controller and orders the data as requested by the AXI master when a single AXI transaction is split into multiple DDR controller transactions, depending on the transfer size.
Page 162: Table 133 Secded Dq Lines At Ddr
Fabric DDR Subsystem 4.6.3.4.4 SECDED The DDR controller supports built-in SECDED capability for correcting single-bit errors and detecting dual-bit errors. The SECDED feature can be enabled. When SECDED is enabled, the DDR controller adds 8 bits of SECDED data to every 64 bits of data. When SECDED is enabled, a write operation computes and stores a SECDED code along with the data, and a read operation reads and checks the data against the stored SECDED code.
Page 163: Fddr Subsystem Features Configuration
Fabric DDR Subsystem REG_DDRC_POWERDOWN_TO_X32 register (Table 59, page 82) has passed, while the controller is idle (except for issuing refreshes). The controller automatically performs the precharge power-down exit on any of the following conditions: • A refresh cycle is required to any rank in the system. •...
Page 164: Burst Mode
Fabric DDR Subsystem Table 134 • Supported Bus Widths Bus Width M2S050/M2GL050 (FG896) M2S150/M2GL150 (FC1152) Full bus width √ √ Half bus width √ √ Quarter bus width – √ 4.6.7 Burst Mode The DDR controller performs burst write operations to DDR memory, depending on the Burst mode selection.
Page 165: Table 136 Dynamically Enforced Bank Constraints
Fabric DDR Subsystem Table 136 • Dynamically Enforced Bank Constraints Row cycle time (t REG_DDRC_T_RC, Minimum time between two successive activates to a Table 46, page 75 given bank. Row precharge command REG_DDRC_T_RP, Minimum time from a precharge command to the next period (t Table 53, page 78...
Page 166: Address Mapping
Fabric DDR Subsystem Table 138 • Dynamic DRAM Global Constraints Write-to-read turnaround REG_DDRC_WR2RD, Table 51, Minimum time to allow between issuing any Write time page 77 command and issuing any Read command Write latency REG_DDRC_WRITE_LATENCY, Time after a Write command that write data should be Table 47, page 76 driven to DRAM.
Page 167: Table 34 Ddrc_Addr_Map_Bank_Cr
Fabric DDR Subsystem • DDRC_ADDR_MAP_BANK_CR, Table 34, page 69 • DDRC_ADDR_MAP_COL_1_CR, Table 35, page 70 • DDRC_ADDR_MAP_COL_2_CR, Table 36, page 70 • DDRC_ADDR_MAP_COL_3_CR, Table 56, page 80 • DDRC_ADDR_MAP_ROW_1_CR, Table 37, page 71 • DDRC_ADDR_MAP_ROW_2_CR, Table 38, page 72 While configuring the registers, ensure that two DDR memory address bits are not determined by the same source address bit.
Page 168 Fabric DDR Subsystem 4.6.10.2 SECDED To enable SECDED mode, set the REG_DDRC_MODE bits to 101 in DDRC_MODE_CR, Table 33, page 68. The PHY_DATA_SLICE_IN_USE_CR register (Table 103, page 103) must be configured to enable data slice 4 of the PHY. The register value REG_DDRC_LPR_NUM_ENTRIES in the performance register, DDRC_PERF_PARAM_1_CR (Table 65, page 84), must be increased by 1 to the value used in Normal...
Page 169: How To Use Fddr In Igloo2 Devices
Fabric DDR Subsystem How to Use FDDR in IGLOO2 Devices This section describes how to use FDDR in the IGLOO2 devices. To configure the IGLOO2 device features and then build a complete system, use the System Builder graphical design wizard in the Libero Software.
Page 170: Figure 82 System Builder - Device Features Tab
Fabric DDR Subsystem Check the Fabric External DDR Memory (FDDR) check box under the Device Features tab and leave the other check boxes unchecked. The following image shows the System Builder - Device Features tab. Figure 82 • System Builder - Device Features Tab Selecting the Fabric External DDR Memory (FDDR) check box in the System Builder performs the following actions: •...
Page 171: Figure 83 Fabric Ddr Memory Configuration
Fabric DDR Subsystem • For more information, refer to the "Address Mapping" section. • Select the I/O Drive Strength as Half Drive Strength or Full Drive Strength, as shown in the following table. The DDR I/O standard is configured as listed in the following table based on this setting.
Page 172: Figure 84 Selecting I/O Standard As Lvcmos18 Or Lpddri
Fabric DDR Subsystem Figure 84 • Selecting I/O Standard as LVCMOS18 or LPDDRI Depending on the application requirement, select the Memory Initialization settings under the Memory Initialization tab as shown in Figure 85 on page 163. • Select the below performance related settings •...
Page 173 Fabric DDR Subsystem • CAS Write Latency (CWL) is defined by DDR3 MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first data in. The overall WRITE latency (WL) is equal to CWL + AL, where CWL is set to 5 clock cycles by default. •...
Page 174: Figure 85 Memory Initialization Configuration
Fabric DDR Subsystem Figure 85 • Memory Initialization Configuration Select the memory timing settings under the Memory Timing tab according to the DDR memory vendor data sheet as shown in the following image. For more details refer to "Configuring Dynamic DRAM Constraints"...
Page 175: Figure 86 Memory Timing Configuration
Fabric DDR Subsystem Figure 86 • Memory Timing Configuration The configurator also provides the option to import and export the register configurations. The configuration settings are stored in eNVM. Configuration files for accessing LPDDR memory on IGLOO2 Evaluation kit can be downloaded from: www.microsemi.com/soc/documents/LPDDR_Emcraft_Config.zip.
Page 176: Figure 87 System Builder - Peripherals Tab
Fabric DDR Subsystem • No Activity clocks for Entry: 320 Memory Timing • Time To Hold Reset Before INIT – 67584 clks • MRD: 4 clks • RAS (Min): 8 clks • RAS (Max): 8192 clks • RCD: 6 clks •...
Page 177: Accessing Fddr From Fpga Fabric Through The Axi Interface
Fabric DDR Subsystem Figure 88 • FDDR Clock Configuration 4.7.1.1 I/O Configuration In the I/O Editor window, configure the I/O settings such as ODT and drive strength. The following image shows the I/O Editor window. Figure 89 • I/O Editor Window 4.7.2 Accessing FDDR from FPGA Fabric through the AXI Interface The AXI master in the FPGA fabric can access the DDR memory through the FDDR subsystem.
Page 178: Figure 90 Fddr Subsystem With Axi Interface
Fabric DDR Subsystem Figure 90 • FDDR Subsystem with AXI Interface HPMS AHB Bus Matrix eNVM FIC_0 FIC_1 FIC _2 Fabric CoreConfigP CoreConfigMaster Master CoreResetP APB_S_PCLK CoreAXI APB_S_PRESET_N AXI_SLAVE APB_SLAVE CORE_RESET_N AXI_S_RMW SDRAM CLK_BASE FAB_PLL_LOCK FDDR IGLOO2 Read, write, and read-modify-write transactions are initiated by the AXI master to read from or write the data to the DDR memory after initializing the FDDR registers.
Page 179: Figure 91 System Builder - Device Features Tab
Fabric DDR Subsystem Go to the System Builder - Device Features tab and check the Fabric External DDR Memory (FDDR) check box and leave the rest of the check boxes unchecked. The following image shows the System Builder - Device Features tab. Figure 91 •...
Page 180: Figure 93 Fabric Ddr Subsystem Configuration Dialog
Fabric DDR Subsystem Figure 93 • Fabric DDR Subsystem Configuration Dialog In the Configuring AMBA_MASTER_0 dialog, select the Interface Type as AXI and then click OK. The following image shows the AMBA Master - Configuration dialog. Figure 94 • AMBA Master Configuration Configure the System Clock and Subsystem clocks in Clocks tab.
Page 181: Figure 95 Clocks Configuration
Fabric DDR Subsystem Figure 95 • Clocks Configuration 10. Navigate to the Memory Map tab giving the required data in the rest of the System Builder tabs. 11. Instantiate the user AXI master logic in the SmartDesign canvas to access the FDDR through the AXI interface.
Page 182: Accessing Fddr From Fpga Fabric Through The Ahb Interface
Fabric DDR Subsystem Figure 96 • SmartDesign Connections (Top Level View) For FDDR AXI throughput, see AC422: SmartFusion2 - Optimizing DDR Controller for Improved Efficiency - Libero v11.7 Application Note. 4.7.3 Accessing FDDR from FPGA Fabric through the AHB Interface The FDDR subsystem can be used to access the DDR memory using the AHB-Lite interface.
Page 183: Figure 97 Fddr With Ahb-Lite Interface
Fabric DDR Subsystem Figure 97 • FDDR with AHB-Lite interface HPMS AHB Bus Matrix eNVM FIC_0 FIC_1 FIC_2 FPGA Fabric CoreConfigP CoreConfigMaster Master CoreResetP APB_S_PCLK CoreAHBLite APB_S_PRESET_N AHB_SLAVE APB_SLAVE CORE_RESET_N SDRAM CLK_BASE FAB_PLL_LOCK FDDR IGLOO2 The procedure for accessing the FDDR from the AHB master in the FPGA fabric is the same as "Accessing FDDR from FPGA Fabric through the AXI Interface"...
Page 184: Ddr Memory Device Examples
Fabric DDR Subsystem DDR Memory Device Examples This section describes how to connect DDR memories to IGLOO2 FDDR_PADs with examples. 4.8.1 Example 1: Connecting 32-Bit DDR2 to FDDR_PADs The following illustration shows DDR2 SDRAM connected to the FDDR of a IGLOO2 device. Micron’s MT47H64M16 is a 128 MB density device with x16 data width.
Page 185: Example 3: Connecting 16-Bit Lpddr To Fddr_Pads With Secded
Fabric DDR Subsystem Figure 99 • x8 DDR3 SDRAM Connection to FDDR FDDR_PADS CASN FDDR_CAS_N FDDR_CKE CLK_P FDDR_CLK CLK_N FDDR_CLK_N FDDR_CS_N FDDR_ODT RASN FDDR_RAS_N FDDR_IMP_CALIB FDDR_RESET_N RSTN FDDR_WE_N FDDR_ADDR[15:0] ADDR[15:0] FDDR_BA[2:0] BA[2:0] FDDR_DM_RDQS[0] FDDR_DQS[0] FDDR_DQS_N[0] DQS# FDDR_DQ[7:0] DQ[7:0] MT41J512M8RA FDDR_DM_RDQS[1] FDDR_DQS[1] FDDR_DQS_N[1] DQS#...
Page 186: Fddr Configuration Registers
Fabric DDR Subsystem Figure 100 • x16 LPDDR1 SDRAM Connection to FDDR FDDR_PADS MT46H32M16LF FDDR_CAS_N CASN FDDR_CKE FDDR_CLK CLK_P FDDR_CLK_N CLK_N FDDR_CS_N FDDR_IMP_CALIB FDDR_RAS_N RASN FDDR_WE_N FDDR_ADDR[12:0] ADDR[12:0] FDDR_BA[1:0] BA[2:0] FDDR_DM_RDQS[1:0] UDM, LDM FDDR_DQS[0] LDQS FDDR_DQS[1] UDQS FDDR_DQ[15:0] DQ[15:0] FDDR_DM_RDQS_ECC FDDR_DQS_ECC MT46H32M16LF FDDR_DQ_ECC[1:0]...
Page 187: Fddr Sysreg Configuration Register Summary
Fabric DDR Subsystem 4.9.1 FDDR SYSREG Configuration Register Summary Table 143 • FDDR SYSREG Address Register Reset Register Name Offset Type Flash Source Description PLL_CONFIG_LOW_1 0x500 PRESETN Comes from SYSREG. Controls the corresponding configuration input of the FPLL. PLL_CONFIG_LOW_2 0x504 PRESETN Comes from SYSREG.
Page 188: Table 145 Pll_Config_Low_2
Fabric DDR Subsystem Table 144 • PLL_CONFIG_LOW_1 [15:6] PLL_FEEDBACK_DIVISOR 0×2 Can be configured to control the corresponding configuration input of the FPLL. Feedback divider value (SSE = 0) (binary value + 1: 00000000 = ÷1, …. 1111111111 = ÷ 1,024) Feedback divider value (SSE = 1) (binary value + 1: 0000000 = ÷1, ….
Page 189: Table 146 Pll_Config_High
Fabric DDR Subsystem Table 146 • PLL_CONFIG_HIGH (continued) Reset Number Name Value Description PLL_MODE_3V3 0×1 Analog voltage selection 1: 3.3 V 0: 2.5 V PLL_MODE_1V2 0×1 Core voltage selection 1: 1.2 V 0: 1.0 V The wrong selection (when operating at 1 V, the jitter is not within the required limit for operation of DDR) may cause the PLL not to function, but will not damage the PLL.
Page 190 Fabric DDR Subsystem Table 147 • FDDR_FACC_CLK_EN [31:1] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. DDR_CLK_EN 0×1 Enables the clock to the DDR memory controller.
Page 191: Table 148 Fddr_Facc_Mux_Config
Fabric DDR Subsystem Table 148 • FDDR_FACC_MUX_CONFIG (continued) Reset Number Name Value Description [2:0] FACC_STANDBY_SEL 0×0 Selects the standby glitch-free multiplexers within the FACC. This is used to allow one of four possible clocks to proceed through to the FDDR subsystem during FACC PLL initialization time (before the FPLL comes into lock).
Page 192: Table 150 Pll_Delay_Line_Sel
Fabric DDR Subsystem Table 150 • PLL_DELAY_LINE_SEL Reset Number Name Value Description [31:4] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 193: Table 153 Fddr_Interrupt_Enable
Fabric DDR Subsystem Table 152 • FDDR_IO_CALIB CALIB_LOCK 0×0 Used in the DDRIO calibration block as an override to lock the codes during intermediate runs. When the firmware receives CALIB_INTRPT, it may choose to assert this signal by prior knowledge of the traffic without going through the process of putting the DDR into self refresh.
Page 194: Table 155 Phy_Self_Ref_En
Fabric DDR Subsystem Table 155 • PHY_SELF_REF_EN Reset Number Name Value Description [31:1] Reserved 0×0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 195: Appendix A: How To Use The Fddr In Smartfusion2 Devices
Fabric DDR Subsystem Table 158 • FDDR_INTERRUPT_SR FDDR_ECC_INT 0×0 Indicates when the ECC interrupt from the FDDR subsystem is asserted. PLL_LOCKLOST_INT 0×0 This bit indicates that a falling edge event occurred on the FPLL_LOCK signal. This indicates that the FPLL lost lock. PLL_LOCK_INT 0×0 This bit indicates that a rising edge event occurred on the FPLL_LOCK...
Page 196: Figure 101 System Builder - Device Features Window
Fabric DDR Subsystem The following image shows the initial System Builder window where you can select the features that you require. For details on how to launch the System Builder wizard and detailed information on how to use it, refer the SmartFusion2 System Builder User Guide.
Page 197: Figure 102 Mss External Ddr Memory Selection
Fabric DDR Subsystem Check the Fabric External Memory (FDDR) check box under the Device Features tab and leave the other check boxes unchecked. The following image shows the System Builder - Device Features tab. Figure 102 • MSS External DDR Memory Selection Navigate to the Memories tab.
Page 198: Figure 103 Fabric Ddr Memory Settings
Fabric DDR Subsystem Figure 103 • Fabric DDR Memory Settings For only LPDDR memory, the I/O standard and I/O calibration settings are available as shown in Figure 84 on page 161. • Select I/O standard as LVCMOS18 or LPDDRI. Note: If LVCMOS18 is selected, all IOs are configured to LVCMOS1.8 except CLK/CLK_N.CLK and CLK_N are configured to LPDDRI standard as they are differential signals.
Page 199 Fabric DDR Subsystem Depending on the application requirement; select the Memory Initialization settings under the Memory Initialization tab as shown in the following image. • Select the below performance related settings • Burst Length can be selected as 4, 8 or 16. Table 134 on page 153 for supported burst lengths.
Page 200: Figure 105 Ddr Memory Initialization Settings
Fabric DDR Subsystem Figure 105 • DDR Memory initialization Settings Select the Memory Timing settings under the Memory Timing tab according to the DDR memory vendor datasheet as shown in the following image. For more details refer to "Configuring Dynamic DRAM Constraints"...
Page 201: Figure 106 Ddr Memory Timing Settings
Fabric DDR Subsystem Figure 106 • DDR Memory Timing Settings The configurator also provides the option to import and export the register configurations. Configuration files for accessing DDR3 memory on SmartFusion2 Development kit can be downloaded from www.microsemi.com/soc/documents/FDDR3_16Bit_SB.zip. Configuration files for accessing LPDDR memory on SmartFusion2 Starter kit can be downloaded from www.microsemi.com/soc/documents/LPDDR_Emcraft_Config.zip.
Page 202: Figure 107 Mss Ddr Fic Subsystem Configuration
Fabric DDR Subsystem • Deep PowerDown enabled: No • No Activity clocks for Entry: 320 Memory Timing • Time To Hold Reset Before INIT - 67584 clks • MRD: 4 clks • RAS (Min): 8 clks • RAS (Max): 8192 clks •...
Page 203: Design Flow Using Smartdesign
Fabric DDR Subsystem Figure 108 • FDDR Clock Configuration 4.10.2 Design Flow Using SmartDesign The following illustration shows the design flow for using the FDDR subsystem to access external DDR memory. The design flow consists of two parts: • Libero flow: This includes configuring the type of DDR memory, choosing fabric master interface type, clocking, and DDR I/O settings.
Page 204 Fabric DDR Subsystem Figure 109 • Design Flow FDDRC Macro Configuration FIC_2 Configuration Libero Design Flow Configure DDR I/O Settings in I/O Editor (for example, ODT, Drive Strength) After FDDR Reset Set the Soft Reset Bit to 0 Configure the FDDR Registers Required Steps for FDDR Initialization...
Page 205: Figure 110 Fabric External Memory Ddr Controller Configurator
Fabric DDR Subsystem Figure 110 • Fabric External Memory DDR Controller Configurator Depending on the application requirement, select the memory settings under the General tab as shown in the image. • Memory Type can be selected as DDR2, DDR3 or LPDDR. •...
Page 206: Figure 111 Fic Configuration
Fabric DDR Subsystem 4.10.2.2 FIC_2 Configuration This is required for initializing the FDDR registers from Cortex-M3 processor. Configure the FIC_2 (Peripheral Initialization) block as shown in the following image to expose the FIC_2_ APB_MASTER interface in Libero SmartDesign. CoreConfigP must be instantiated in SmartDesign and make the connections illustrated in the FIC_2 Configurator.
Page 207: Use Model 1: Accessing Fddr From Fpga Fabric Through Axi Interface
Fabric DDR Subsystem 4.10.3 Use Model 1: Accessing FDDR from FPGA Fabric Through AXI Interface The AXI master in the FPGA fabric can accesses the DDR memory through the FDDR subsystem, as shown in the following illustration. The FDDR registers are configured from FPGA fabric through the APB interface.
Page 208: Figure 114 Fddr Configuration
Fabric DDR Subsystem Figure 114 • FDDR Configuration Instantiate the clock resources (FAB_CCC and chip oscillators) in the SmartDesign canvas and configure, as required. In this example, the fabric CCC is configured to generate 111 MHz, as shown in the following image. Microsemi ProprietaryUG0446 User Guide Revision 7.0...
Page 209: Figure 115 Fabric Ccc Configuration
Fabric DDR Subsystem Figure 115 • Fabric CCC Configuration Instantiate user AXI master logic in the SmartDesign canvas to access the FDDR through the AXI interface. Ensure that the AXI master logic accesses the FDDR after configuring the FDDR registers from the APB master.
Page 210: Use Model 2: Accessing Fddr From Fpga Fabric Through Ahb Interface
Fabric DDR Subsystem To verify the design in Libero SoC, create a SmartDesign testbench project and instantiate a DDR memory model provided by the DDR memory vendor. Simulate the design and observe the AXI read and write transactions. Note: The FDDR subsystem can be configured using the Cortex-M3 processor without having an APB master in the FPGA fabric.
Page 211: Figure 118 Fic_2 Configuration
Fabric DDR Subsystem Figure 118 • FIC_2 Configuration Configure MSSCCC for the FIC_0 clock, as shown in the following image. The FIC_0 clock is configured to 111 MHz. Figure 119 • MSS CCC Configuration Instantiate the DDR Memory Controller macro in the SmartDesign canvas. Configure the FDDR and select the dual AHB interface, as shown in the following image.
Page 212: Figure 120 Fddr Configuration
Fabric DDR Subsystem Figure 120 • FDDR Configuration Depending on the application requirement select the memory settings. For more details refer to 3 and 4 in the "Design Flow Using System Builder". Instantiate the clock resources (FCCC and chip oscillators) in the SmartDesign canvas and configure, as required.
Page 213: Figure 121 Fabric Ccc Configuration
Fabric DDR Subsystem Figure 121 • Fabric CCC Configuration Instantiate CoreConfigP in the SmartDesign canvas and configure for FDDR, as shown in the following image. Make the FIC_2 and FDDR APB interface connections to CoreConfigP. Figure 122 • CoreConfigP IP Configuration 10.
Page 214: Figure 123 Coreconfigp Ip Configuration
Fabric DDR Subsystem Figure 123 • CoreConfigP IP Configuration 11. Instantiate user AHB master logic in the SmartDesign canvas to access the FDDR through the AHB interface. The AHB master clock frequency should be the same as the FDDR DDR_FIC clock frequency.
Page 215: Appendix B: Register Lock Bits Configuration
Fabric DDR Subsystem Figure 124 • SmartDesign Canvas 14. To verify the design in Libero SoC, create a SmartDesign testbench project and instantiate a DDR memory model provided by the DDR memory vendor. Simulate the design and observe the AHB read and write transactions.
Page 216: Locking And Unlocking A Register
Fabric DDR Subsystem Set the lock bit value to 1 to indicate that the register can be written to (unlocked) and to 0 to indicate that the register cannot be written to (locked). Lines starting with # or ; are comments. Empty lines are allowed in the lock bit configuration file. The following figure shows the lock bit configuration file.
Page 217 Fabric DDR Subsystem Regenerate the bitstream. Microsemi ProprietaryUG0446 User Guide Revision 7.0...
Page 218: Ddr Bridge
DDR Bridge DDR Bridge The DDR bridge facilitates multiple AHB bus masters to access a single AXI slave and optimizes read and write operations from multiple AHB masters to a single external DDR memory. The SmartFusion2 and IGLOO2 devices have three instances of the DDR bridge, one each for the MSS/HPMS, FDDR, and MDDR subsystems, as shown in the following image.
Page 219: Functional Description
DDR Bridge masters are fixed, as shown in the following table. The DDR bridges in the MDDR and FDDR subsystems support only two AHB interfaces out of four and these can be used for user implemented AHB masters. Table 163 • SmartFusion2 and IGLOO2 FPGA DDR Bridge Interface DDR Bridge Sub- AHB Interface 0...
Page 220: Details Of Operation
DDR Bridge Figure 128 • DDR Bridge Functional Block Diagram AHB Interface 0 to e 0 to Read Read connect with AHB Master connect with AHB Master Buffer Buffer Arbiter AHB Interface 1 to e 1 to Write Access rite Access WCB and Read and Read connect with AHB Master...
Page 221: Figure 129 Wcb Operation
DDR Bridge Figure 129 • WCB Operation Start Write request = 1 Bufferable Write Request? Write address is matching with WCB tag/WCB empty? Buffer the data based on WCB tag WCB full/ timeout Write the data in WCB to AXI slave 5.1.2.2 Read Buffer The DDR bridge has a read buffer for each master to hold the fetched DDR burst data.
Page 222: Figure 130 Flow Chart For Read Operation
DDR Bridge Figure 130 • Flow Chart for Read Operation Start Read request = 1 Other master is holding the read transaction? Non bufferable read Read buffer is request? empty? Send read request to arbiter. Make AHB master Send read request to arbiter with burst size Read address is ready High.
Page 223: How To Use Ddr Bridge In Igloo2 Device
DDR Bridge write into WCB, but the DDR bridge does not write this data until the previous write transactions are completed to the external DDR memory. 5.1.2.3.2 Read Access Controller The read access controller (RAC) arbitrates read requests from read buffers and grants access to one of the requesting masters depending on its priority.
Page 224: Configuring The Ddr Bridge
DDR Bridge Figure 131 • System Builder - Device Features Window Navigate to the HPMS Options tab in the System Builder wizard. For more information about how to use MDDR in the SmartFusion2 devices, refer to "Appendix A: How to Use DDR Bridge in SmartFusion2 Device"...
Page 225: High-Speed Data Transactions From Hpdma
DDR Bridge read/write buffers. The DDR bridge configurator allows to select the size of read/write buffers as 32 bytes or 16 bytes. Figure 132 • Configuring HPMS DDR Bridge for HPDMA 5.2.1.2 Configurations for the DDR Bridge in the MDDR or FDDR Subsystems The DDR bridge in the MDDR or FDDR subsystem can be configured using the DDR_FIC registers listed Table 165 on page 216.
Page 226: Selecting Non-Bufferable Region
DDR Bridge 5.2.3 Selecting Non-Bufferable Region This section describes the use of the non-bufferable region selection in the DDR bridge. The buffering creates more latency in the applications which access non-continuous memory locations. In such cases non-bufferable region selection provides high throughput than bufferable. The application uses only 256 MB of memory segment (0xB000_0000 to 0XBFFF_FFFF) as non-bufferable and the other memory region as bufferable.
Page 227: Ddr Bridge Control Registers In Mddr And Fddr
DDR Bridge Table 164 • SYSREG Control Registers (continued) Register Flash Write Register Name Type Protect Reset Source Description MSSDDR_FACC1_CR RW-P Field CC_RESET_N HPMS DDR fabric alignment clock controller 1 configuration register. DDR Bridge Control Registers in MDDR and FDDR The following table lists HPMS DDR bridge control registers in the MDDR and FDDR.
Page 228: Use Model 1: High Speed Data Transactions From Cortex-M3 Processor
DDR Bridge The default address is 0×A000. If the non-bufferable region size and address is left as default then the 64 KB memory from 0×A0000000 address to 0×A0010000 address will be non-bufferable. • Enable or disable respective buffers allocated for each master: The selection of disabling the write/read buffer makes all transactions without buffering.
Page 229: Use Model 2: Selecting Non-Bufferable Region
DDR Bridge Figure 136 • Configuring MSS DDR Bridge for Use Model 1 5.5.2 Use Model 2: Selecting Non-Bufferable Region This use model shows the use of the non-bufferable region selection in the DDR bridge. The buffering creates more latency in the applications which access non-continuous memory locations. In such cases non-bufferable region selection provides high throughput than bufferable.
Page 230: Soft Memory Controller Fabric Interface Controller
Soft Memory Controller Fabric Interface Controller Soft Memory Controller Fabric Interface Controller The SmartFusion2 and IGLOO2 soft memory controller fabric interface controller (SMC_FIC) is used to access external bulk memories other than DDR through the FPGA fabric. The SMC_FIC can be used with a soft memory controller for the MSS/HPMS to access memories such as SDRAM, flash, and SRAM.
Page 231: Functional Description
Soft Memory Controller Fabric Interface Controller Functional Description The SMC_FIC receives 64-bit AXI transactions from the MSS/HPMS DDR bridge and converts them into 64-bit AXI or 32-bit AHB-Lite transactions to the SMC in the FPGA fabric. The following illustration shows the block diagram of the SMC_FIC.
Page 232 Soft Memory Controller Fabric Interface Controller Table 166 • SMC_FIC 64-bit AXI Port List (continued) Signal Direction Polarity Description MDDR_SMC_AXI_M_BREADY Output High Indicates whether or not the master can accept the response information. 1: Master ready 0: Master not ready MDDR_SMC_AXI_M_AWVALID Output High...
Page 233 Soft Memory Controller Fabric Interface Controller Table 166 • SMC_FIC 64-bit AXI Port List (continued) Signal Direction Polarity Description MDDR_SMC_AXI_M_AWLEN[3:0] Output Indicates burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
Page 234 Soft Memory Controller Fabric Interface Controller Table 166 • SMC_FIC 64-bit AXI Port List (continued) Signal Direction Polarity Description MDDR_SMC_AXI_M_ARLEN[3:0] Output Indicates burst length. The burst length gives the exact number of transfers in a burst. 0000: 1 0001: 2 0010: 3 0011: 4 0100: 5...
Page 235: Table 167 Smc_Fic 32-Bit Ahb-Lite Port List
Soft Memory Controller Fabric Interface Controller Table 166 • SMC_FIC 64-bit AXI Port List (continued) Signal Direction Polarity Description MDDR_SMC_AXI_M_ARLOCK[1:0] Output Indicates lock type. This signal provides additional information about the atomic characteristics of the read transfer. 00: Normal access 01: Exclusive access 10: Locked access 11: Reserved...
Page 236: How To Use Smc_Fic In Igloo2 Device
Soft Memory Controller Fabric Interface Controller Table 167 • SMC_FIC 32-bit AHB-Lite Port List (continued) Signal Direction Polarity Description MDDR_SMC_AHB_M_HSIZE[1:0] Output Indicates the size of the transfer. 00: Byte 01: Half word 10: Word MDDR_SMC_AHB_M_HWDATA[31:0] Output The write data bus is used to transfer data during write operations.
Page 237: Figure 141 Hpms Smc_Fic Subsystem Configuration
Soft Memory Controller Fabric Interface Controller Figure 141 • HPMS SMC_FIC Subsystem Configuration Configure CoreSDR_AXI to match the external memory parameters. Figure 142 • CoreSDR_AXI Configuration Navigate to the Memory Map tab giving the required data in the rest of the System Builder tabs. Click Finish.
Page 238: Sysreg Control Register For Smc_Fic
Soft Memory Controller Fabric Interface Controller The System Builder creates a SmartDesign with CoreSDR_AXI connected to SMC_FIC and exposes the AHB mirrored master interface which is connected to FIC_0 to access the HPDMA configuration registers. Microsemi provides CoreHPDMACtrl IP to configure the HPDMA. Connect the CoreHPDMACtrl IP to the AHB mirrored master interface of System Builder created design or connect user AHB master logic to configure the HPDMA to perform the DMA transactions from SDRAM.
Page 239: Use Model 1: Accessing Sdram From Mss Through Coresdr_Axi
Soft Memory Controller Fabric Interface Controller 6.4.2 Use Model 1: Accessing SDRAM from MSS Through CoreSDR_AXI This use model describes how to use the SMC_FIC to access external SDR memory from MSS. It uses the AXI interface of SMC_FIC to connect to CoreSDR_AXI. CoreSDR_AXI is an AXI-based SDR memory controller.
Page 240: Figure 145 Subsystem Connections In Smartdesign
Soft Memory Controller Fabric Interface Controller Figure 145 • Subsystem Connections in SmartDesign Refer to the Accessing External SDRAM through Fabric tutorial, which describes the steps for creating a design that accesses external SDR memory from the Cortex-M3 processor. The tutorial also explains the steps for simulating the design in Libero SoC.

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Microsemi igloo2

Microchip Technology Microsemi SmartFusion2 User Manual

1 Revision History

2 Overview

3 MDDR Subsystem

Appendix A: How to Use the MDDR in Smartfusion2

4 Fabric DDR Subsystem

Appendix A: How to Use the FDDR in Smartfusion2 Devices

Appendix B: Register Lock Bits Configuration

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