Figure 28 Mddr With Single Ahb-Lite Interface; Table 23 Mddr Throughput (For Ahb) - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Figure 28 • MDDR with Single AHB-Lite Interface
D
D
DDR R
SDRAM
I
O
The procedure for accessing the MDDR from AHB master in the FPGA fabric is the same as in
"Accessing MDDR from FPGA Fabric through the AXI Interface" section on page
following:
• Configure the AMBA Master Interface Type as AHB-Lite in the HPMS DDR FIC Subsystem in the
Peripherals tab of the System Builder wizard.
Table 23, page 49 lists the MDDR throughput for the following configuration:
• Fabric Interface: AHB
• MDDR Mode: DDR3
• Fabric Clock to MDDR Clock Ratio: 1:4
• PHY Width: 16 and 32
• Clock Frequency: 80 MHz
The other parameters are configured similar to the MDDR configuration in
Optimizing DDR Controller for Improved Efficiency - Libero v11.7 Application
Table 23 • MDDR Throughput (for AHB)
MDDR-Fabric
Interface-Memory
MDDR_AHB-DDR3
D
D
AXI
R
Transaction
Controller
P
DDR
H
Controller
Y
APB Config
Reg
Master
AHB_Lite
Slave 1
Slave n
IGLOO2
Frequency Ratio
( ) PHY Width
CLK_BASE:FDDR_CLK
1:4 PHY_16
80 MHz:320 MHz
PHY_32
Microsemi Proprietary UG0446 User Guide Revision 7.0
MDDR
HPMS DDR
Bridge
DDR_FIC
AHB Bus Matrix
FIC_0
AHB
CoreConfigMaster
AC422: SmartFusion2 -
Write Transaction BW
(MB/sec)
80 MB
80 MB
HPMS
HPDMA
eNVM
FIC_1 APB_2
CoreConfigP
Fabric
43—except for the
Note.
Read Transaction BW
(MB/sec)
79 MB
79 MB
49