Figure 114 Fddr Configuration - Microchip Technology Microsemi SmartFusion2 User Manual

Fpga high speed ddr interfaces
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Fabric DDR Subsystem
Figure 114 • FDDR Configuration
3.
Instantiate the clock resources (FAB_CCC and chip oscillators) in the SmartDesign canvas and
configure, as required. In this example, the fabric CCC is configured to generate 111 MHz, as shown
in the following image.
Microsemi ProprietaryUG0446 User Guide Revision 7.0
197

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