Figure 115 Fabric Ccc Configuration; Figure 116 Smartdesign Canvas - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
Figure 115 • Fabric CCC Configuration
4. Instantiate user AXI master logic in the SmartDesign canvas to access the FDDR through the AXI
interface. Ensure that the AXI master logic accesses the FDDR after configuring the FDDR registers
from the APB master. The AXI master clock frequency should be same as FDDR DDR_FIC clock
frequency.
5. Instantiate user APB master logic in the SmartDesign canvas to configure the FDDR registers
through the APB interface.
6. Connect the AXI master to the FDDR AXI slave interface. Connect the APB master to the FDDR
APB slave interface through CoreAPB.
7. Make the other connections in the SmartDesign canvas, as shown in the following image.
Figure 116 • SmartDesign Canvas
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