Initialization - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 8 • MDDR APB Slave Interface Signals (continued)
Signal Name
MDDR_APB_S_PWRITE
MDDR_APB_S_PADDR[10:2]
MDDR_APB_S_PWDATA[15:0]
3.5.3

Initialization

After power-up, the MDDR needs to have all of the configuration registers written to establish the
operating modes of the blocks. When using the System Builder design flow through Libero SoC, this is all
handled for the user through the use of the System Builder module. All of the configuration register
values are selected by the user and stored in a special portion of the embedded non-volatile memory
(eNVM). Before the MDDR subsystem is active, it goes through an initialization phase and this process
starts with a reset sequence. For DDR3 memories, the initialization phase also includes ZQ calibration
and DRAM training.
3.5.3.1 Reset Sequence
The following illustration shows the reset sequence for the MDDR subsystem from the power on reset
stage. The MDDR subsystem comes out of reset after MPLL Lock is asserted by the MSS/HPMS_CCC.
De-assertion of MDDR_AXI_RESET_N signifies the end of the reset sequence. The MDDR reset can be
generated by asserting MDDR_CTLR_SOFTRESET bit in
performs external DRAM memory reset and initialization as per the JEDEC specification, including reset,
refresh, and mode registers.
3.5.3.2 DDRIO Calibration
Each DDRIO has an ODT feature, which is calibrated depending on the DDR I/O standard. DDR I/O
calibration occurs after the DDR I/Os are enabled. If the impedance feature is enabled, impedance can
be programmed to the desired value in three ways:
• Calibrate the ODT/driver impedance with a calibration block (recommended)
• Calibrate the ODT/driver impedance with fixed calibration codes
• Configure the ODT/driver impedance to the desired value directly
The system register, MDDR_IO_CALIB_CR, can be configured for changing the ODT value to the
desired value.
The I/O calibration is always enabled when the DDR subsystem is configured for DDR2 and DDR3
memories.
The I/O calibration can be disabled or enabled using the DDR configurator when the DDR subsystem is
configured for LPDDR memories.
Note: If I/O calibration is enabled, all I/Os in the DDR bank are calibrated even though the DDR controller is not
using all I/Os in the bank.
For more information on DDR I/O calibration, refer to the Configurable ODT and Driver Impedance
section of the I/Os chapter in the
Guide.
Direction Polarity
Input High
Input
Input
UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User
Microsemi Proprietary UG0446 User Guide Revision 7.0
Description
Indicates APB write control signal form Fabric
master
Indicates APB address initiated by Fabric master.
Indicates APB write data from Fabric master.
SOFT_RESET_CR to 1. The DDR controller
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