Table 64 Ddrc_Zq_Short_Int_Refresh_Margin_2_Cr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 63 • DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR (continued)
[3:0] REG_DDRC_REFRESH_MARGIN
Table 64 • DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR
Bit
Number Name
[31:8] Reserved
[7:0] REG_DDRC_T_ZQ_SHORT_INTERVAL_X1024
Table 65 • DDRC_PERF_PARAM_1_CR
Bit
Number Name
[31:16] Reserved
Rese
t
Valu
e Description
0×0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
Microsemi Proprietary UG0446 User Guide Revision 7.0
0×02 Threshold value in number of clock cycles
before the critical refresh or page timer expires.
A critical refresh is to be issued before this
threshold is reached. Microsemi recommends
using the default value.
Unit: Multiples of 32 clocks.
Reset
Value Description
0×0 Software should not rely on the value of a
reserved bit. To provide compatibility with
future products, the value of a reserved bit
should be preserved across a read-modify-
write operation.
0×0 20 bits are split into two registers.
[19:12] bits of
REG_DDRC_T_ZQ_SHORT_INTERVAL_X10
24.
Average interval to wait between automatically
issuing ZQ calibration short (ZQCS)
commands to DDR3 devices. Not considered if
REG_DDRC_DIS_AUTO_ZQ = 1.
Units: 1,024 clock cycles
This is only present for implementations
supporting DDR3 devices.
84