Figure 5 Axi Transaction Controller Block Diagram; Table 10 Priority Level Configuration - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Figure 5 • AXI Transaction Controller Block Diagram
AXI Slave
64-Bit AXI Bus
Interface 0
from MSS/HPMS
DDR Bridge
AXI Slave
64-Bit AXI Bus
Interface 1
from DDR_FIC
The AXI transaction controller comprises four major blocks:
• AXI slave interface
• Priority block
• Transaction handler
• Reorder buffer
3.5.4.2.1 AXI Slave Interfaces
The AXI transaction controller has two 64-bit AXI slave interfaces: one from the MSS/HPMS DDR bridge
and the other from DDR_FIC. Each of the AXI slave ports is 64 bits wide and is in compliance with the
standard AXI protocol. Each transaction has an ID related to the master interface. Transactions with the
same ID are completed in order, while the transactions with different read IDs can be completed in any
order, depending on when the instruction is executed by the DDR controller. If a master requires ordering
between transactions, the same ID should be used.
The AXI slave interface has individual read and write ports. The read port queues read AXI transactions
and it can hold up to four read transactions. The write port handles only one write transaction at a time
and generates the handshaking signals on the AXI interface.
3.5.4.2.2 Priority Block
The priority block prioritizes AXI read/write transactions and provides control to the transaction handler.
AXI read transactions have higher priority. The default priority ordering is listed as follows:
1. Reads from the slave port of the MSS/HPMS DDR bridge
2. Reads from the slave port of DDR_FIC
3. Writes from the slave port of the MSS/HPMS DDR bridge
4. Writes from the slave port of DDR_FIC
The fabric master through DDR_FIC can be programmed to have a higher priority by configuring the
PRIORITY_ID and PRIORITY_ENABLE_BIT bit fields in the
Priority levels to other masters can be programmed as well, as shown in the following table.
Table 10 • Priority Level Configuration
Transactions
SmartFusion 2
Reads from I - Cache
Reads from DSG bus
Reads from HPDMA/AHB bus
Reads from Fabric master having
the ID as PRIORITY_ID
AXI Transaction Controller
Priority Block
Default
Priorities
(Type-0) Priorities
PRIORITY_ENABLE_BIT=01
(Type 1)
1 2
2 3
3 4
4 3
Microsemi Proprietary UG0446 User Guide Revision 7.0
Transaction
Handler
DDR
Controller
Re-Order Buffer
DDRC_AXI_FABRIC_PRI_ID_CR
PRIORITY_ENABLE_BIT=10/11
(Type 2/3)
2
3
4
1
PHY
register.
20