Table 9 Mddr_Clk To Fpga Fabric Clock Ratios - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
• Dual AHB-32 bit interfaces
If the AXI-64 interface is selected, the DDR_FIC acts as an AXI to AXI synchronous bridge. In this mode,
DDR_FIC provides FPGA fabric masters to access the MDDR subsystem through locked transactions.
For this purpose, a user configurable 20-bit down counter keeps track of the duration of the locked
transfer. If the transfer is not completed before the down counter reaches zero, a single clock cycle pulse
interrupt is generated to the fabric interface.
If single or dual AHB-32 interfaces are selected, DDR_FIC converts the single/dual 32-bit AHBL master
transactions from the FPGA fabric to 64-bit AXI transactions. In this mode the DDR bridge, embedded as
part of the DDR_FIC, is enabled. The DDR bridge has an arbiter, which arbitrates read and write
requests from the two AHB masters on a round robin priority scheme. Refer to the
Registers in MDDR and FDDR" chapter on page 216
The DDR_FIC input interface is clocked by the FPGA fabric clock and the MDDR is clocked by
MDDR_CLK from the MSS/HPMS CCC. Clock ratios between MDDR_CLK and DDR_FIC clock can
vary. The following table lists supported ratios. Clock ratios can be configured through Libero System-on-
Chip (SoC) software or through system register MSSDDR_FACC1_CR. For more information, refer to
the "MDDR Configuration Registers" section on page
Table 9 • MDDR_CLK to FPGA Fabric Clock Ratios
DIVISOR_A[1:0]
00
00
00
00
00
01
01
01
01
11
11
11
3.5.4.2 AXI Transaction Controller
The AXI transaction controller receives 64-bit AXI transactions from various masters (MSS/HPMS DDR
bridge and DDR_FIC) and translates them into DDR controller transactions. The following illustration
shows the block diagram of the AXI transaction controller interfaced with the DDR controller.
The AXI transaction controller performs arbitration of the read/write requests initiated by AXI compliant
masters.
FIC64_DIVISOR[2:0]
000
001
010
100
101
000
001
010
100
000
001
010
Microsemi Proprietary UG0446 User Guide Revision 7.0
for a detailed description.
61.
MDDR_CLK: FPGA FABRIC Clock Ratio
1:1
2:1
4:1
8:1
16:1
2:1
4:1
8:1
16:1
3:1
6:1
12:1
"DDR Bridge Control
19