Table 114 Ddr_Fic_Hpb_Err_Addr_2_Sr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 114 • DDR_FIC_HPB_ERR_ADDR_2_SR
Bit
Number Name
[31:16] Reserved
[15:0] DDR_FIC_M1_ERR_ADD
Table 115 • DDR_FIC_SW_ERR_ADDR_1_SR
Bit
Number Name
[31:16] Reserved
[15:0] DDR_FIC_M2_ERR_ADD
Table 116 • DDR_FIC_SW_ERR_ADDR_2_SR
Bit
Number Name
[31:16] Reserved
[15:0] DDR_FIC_M2_ERR_ADD
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit
should be preserved across a read-modify-write operation.
0×0 32 bits are split into two registers.
[31:16] bits of DDR_FIC_M1_ERR_ADD
Tag of write buffer for which error response is received is placed
in this register. The following values are updated in this register
as per buffer size:
Buffer size
16 bytes: 28 bit TAG value is loaded to [31:4] and 0000 to [3:0]
32 bytes: upper 27 bits of TAG is loaded to [31:5] and 00000 to
[4:0]
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit
should be preserved across a read-modify-write operation.
0×0 32 bits are split into two registers.
Lower 16 bits.
Tag of write buffer for which error response is received is placed in
this register. The following values are updated in this register as
per buffer size:
Buffer size: DDR_FIC_M2_ERR_ADD[31:0]
16 bits: TAG, 0000
32 bits: TAG[27:1], 00000
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a reserved
bit should be preserved across a read-modify-write operation.
0×0 32 bits are split into two registers.
[31:16] bits of DDR_FIC_M2_ERR_ADD
Tag of write buffer for which error response is received is placed
in this register. The following values are updated in this register
as per buffer size:
Buffer size
16 bytes: 28 bit TAG value is loaded to [31:4] and 0000 to [3:0]
32 bytes: upper 27 bits of TAG is loaded to [31:5] and 00000 to
[4:0]
Microsemi Proprietary UG0446 User Guide Revision 7.0 109