Figure 37 Axi Incr16 Write Transaction; Figure 38 Ddr Controller Command Sequence For Axi Incr16 Write Transaction; Figure 39 Axi Incr-16 Read Transaction And Corresponding Ddr Controller Commands - Microchip Technology Microsemi SmartFusion2 User Manual

Fpga high speed ddr interfaces
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MDDR Subsystem
Figure 37 • AXI INCR16 Write Transaction
DDR write controls
Figure 38 • DDR Controller Command Sequence for AXI INCR16 Write Transaction
MDDR_CAS_N
MDDR_CKE
MDDR_CLK
MDDR_CLK_N
MDDR_CS_N
MDDR_ODT
MDDR_RAS_N
MDDR_RESET_N
MDDR_WE_N
MDDR_ADDR
MDDR_BA
MDDR_DM_RDQS
MDDR_DQS
MDDR_DQS_N
MDDR_DQ
MDDR_DQS_TMATCH_0_IN
MDDR_DQS_TMATCH_0_OUT
mddr_dqs_tmatch_0_out
Figure 39 • AXI INCR-16 Read Transaction and Corresponding DDR Controller Commands
MDDR_CAS_N
MDDR_CKE
MDDR_CLK
MDDR_CLK_N
MDDR_CS_N
MDDR_ODT
MDDR_RAS_N
MDDR_RESET_N
MDDR_WE_N
0000
MDDR_ADDR
0
MDDR_BA
MDDR_DM_RDQS
MDDR_DQS
MDDR_DQS_N
MDDR_DQ
MDDR_DQS_TMATCH_0_IN
MDDR_DQS_TMATCH_0_OUT
mddr_dqs_tmatch_0_out
DDR write controls
CLK
0
ARID
0
ARADDR
00000000
f
00000000
ARLEN
3
ARSIZE
0
0
ARLOCK
1
ARBURST
ARVALID
ARREADY
0
RID
RDATA
RVALID
RLAST
RREADY
0
RESP
0
1
CLK_CNT
CLK
0
AWID
0
0
AWADDR
f
AWLEN
3
AWSIZE
0
AWLOCK
1
AWBURST
AWVALID
AWREADY
WID
WSTRB
ff
WLAST
WVALID
0
1 2
3
4
WDATA
WREADY
BID
RESP
BVALID
BREADY
0
1
2
3 4
5
6
7 8
0000
0008
0010
0
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
0
0
1
2
0008
0010
0
Read transac on to
DDR Memory ini ated
0
0
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Microsemi Proprietary UG0446 User Guide Revision 7.0
5 6
7
8
9
10
11
12
13 14
9
10 11 12
13
14 15 16
18 19 20
21
22 23 24
17
0020
0028
0018
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
0
0
0
0
0
0
3
4
5
6
7
8
9
0018
0020
0028
0030
0038
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
15
16
0
0
25
26 27 28
29
30 31 32
33
34
0038
0030
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
0
0
0
0
0
10
11
12
13
14
15
16
Refer
Figure 1-36
8
9
10
11
12
13
14
CLK Cycles for comple ng
transac on
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
15
16
47
48
49
50
54

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