Fddr Configuration Registers; Figure 100 X16 Lpddr1 Sdram Connection To Fddr; Table 142 Address Table For Register Interfaces - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
Figure 100 • x16 LPDDR1 SDRAM Connection to FDDR
FDDR_PADS
FDDR_CAS_N
FDDR_CLK_N
FDDR_CS_N
FDDR_IMP_CALIB
FDDR_RAS_N
FDDR_WE_N
R
FDDR_ADDR[12:0]
FDDR_BA[1:0]
FDDR_DM_RDQS[1:0]
FDDR_DQS[0]
FDDR_DQS[1]
FDDR_DQ[15:0]
FDDR_DM_RDQS_ECC
FDDR_DQS_ECC
FDDR_DQ_ECC[1:0]
FDDR_DQS_TMATCH_0_IN
FDDR_DQS_TMATCH_0_OUT
FDDR_DQS_TMATCH_ECC_IN
FDDR_DQS_TMATCH_ECC_OUT
4.9

FDDR Configuration Registers

This section provides FDDR subsystem registers along with the address offset, functionality, and bit
definitions. The registers are categorized based on the controller blocks in the FDDR subsystem.
The following table lists the categories of registers and their offset addresses.
Table 142 • Address Table for Register Interfaces
Registers
DDR Controller Configuration Register,
PHY Configuration Register Summary,
DDR_FIC Configuration Register Summary,
FDDR SYSREG Configuration Register Summary,
Reserved
Note: The FDDR SYSREG configuration registers can be locked to prevent them from being overwritten by the
masters that have access to these registers. For information on how to lock/unlock these registers, see
"Appendix B: Register Lock Bits Configuration" on page
FDDR_CKE
FDDR_CLK
Table 28, page 63
Table 102, page 103
Table 104,
Table 143,
Microsemi ProprietaryUG0446 User Guide Revision 7.0
Address Offset Space
0x000:0x1FC
0x200:0x3FC
page 103 0x400:0x4FC
page 176 0x500:0x5FC
0x600:0x7FC
204.
MT46H32M16LF
CASN
CKE
CLK_P
CLK_N
CSN
RASN
WEN
ADDR[12:0]
BA[2:0]
UDM, LDM
LDQS
UDQS
DQ[15:0]
MT46H32M16LF
CASN
CKE
CLK_P
CLK_N
CSN
RASN
WEN
ADDR[12:0]
BA[2:0]
LDM
LDQS
DQ[1:0]
175