Figure 17 System Builder - Peripherals Tab - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
• Deep PowerDown enabled: No
• No Activity clocks for Entry: 320
• Memory Timing
• Time To Hold Reset Before INIT: 67584 clks
• MRD: 4 clks
• RAS (Min): 8 clks
• RAS (Max): 8192 clks
• RCD: 6 clks
• RP: 7 clks
• REFI: 3104 clks
• RC: 3 clks
• XP: 3 clks
• CKE: 3 clks
• RFC: 79 clks
• FAW: 0 clks
7. Navigate to the Peripherals tab. The Peripherals tab allows configuration of the Fabric AMBA
Master and Fabric AMBA Slave required for the design. Drag and drop the required master/slave to
the corresponding subsystem. The following image shows the Peripherals tab. Drag and drop the
Fabric Master core to the HPMS DDR FIC Subsystem. This allows to the interface to be
configured as AXI or single AHB-Lite. On completing the configuration, the selected interface is
enabled. The user logic in the FPGA fabric can access the DDR memory through the MDDR using
these interfaces.
Figure 17 • System Builder - Peripherals Tab
8. Navigate to the Clocks tab. The Clocks tab allows configuration of the System Clock and
subsystem clocks.The MDDR subsystem operates on MDDR_CLK, which comes from HPMS_CCC.
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