Use Model 1: Accessing Fddr From Fpga Fabric Through Axi Interface; Figure 113 Fddr With Axi Interface - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
4.10.3 Use Model 1: Accessing FDDR from FPGA Fabric Through AXI
Interface
The AXI master in the FPGA fabric can accesses the DDR memory through the FDDR subsystem, as
shown in the following illustration. The FDDR registers are configured from FPGA fabric through the APB
interface. The APB master in the FPGA fabric asserts a ready signal to the AXI master, indicating
successful initialization of the DDR memory.
Read, write, and read-modify-write transactions are initiated by the AXI master to read or write the data
into the DDR memory after receiving a ready signal from the APB master.
Figure 113 • FDDR with AXI Interface
SmartFusion2
Use the following steps to access the FDDR from the AXI master in the FPGA fabric:
1. Instantiate the DDR Memory Controller macro in the SmartDesign canvas.
2. Configure the FDDR and select the AXI interface, as shown in the following image. In this example,
the design is created to access DDR3 memory with a 32-bit data width. The FDDR clock is
configured to 333 MHz and DDR_FIC is configured to 111 MHz.
FPGA Fabric
AXI Master
CCC
User Logic
APB_S_PCLK
APB_S_PRESET_N
AXI_S_RMW
CORE_RESET_N
CLK_BASE
FAB_PLL_LOCK
Microsemi ProprietaryUG0446 User Guide Revision 7.0
APB Master
Logic
PADs
DDR
I/O
FDDR
DDR
SDRAM
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