Figure 102 Mss External Ddr Memory Selection; Table 161 Supported Address Width Range For Row, Bank And Column Addressing In Ddr/Lpddr; Table 162 Ddr I/O Standard Is Configured Based On I/O Drive Strength Setting - Microchip Technology Microsemi SmartFusion2 User Manual

Fpga high speed ddr interfaces
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Fabric DDR Subsystem
1.
Check the Fabric External Memory (FDDR) check box under the Device Features tab and leave
the other check boxes unchecked. The following image shows the System Builder - Device
Features tab.
Figure 102 • MSS External DDR Memory Selection
2.
Navigate to the Memories tab. Depending on the application requirement, select the memory
settings under the General tab as shown in the following image.
Memory Type can be selected as DDR2, DDR3 or LPDDR.
The Data width can be selected as 32- bit, 16-bit, or 8-bit. Refer
supported data widths for various SmartFusion2 device packages.
The SECDED (ECC) can be enabled or disabled.
Address Mapping - The register settings to perform mapping to system address bits for various
Row, Bank and Column combinations are automatically computed by the configurator using
address mapping option.
Column.
Table 161 • Supported Address Width Range for Row, Bank and Column Addressing in DDR/LPDDR
Width
Row Address
Bank Address
Column Address
Select the I/O Drive Strength as Half Drive Strength or Full Drive Strength as shown in
Figure 3,
on this setting.
Table 162 • DDR I/O Standard is Configured Based on I/O Drive Strength Setting
I/O Drive Strength
Half Drive Strength
Full Drive Strength
Table 161,
DDR2
12-16
2-3
9-12
page 17. The DDR I/O standard is configured as listed in
Memory Type
DDR2
SSTL18I
SSTL18II
Microsemi ProprietaryUG0446 User Guide Revision 7.0
page 186 shows the supported range for Row, Bank and
DDR3
12-16
2-3
9-12
DDR3
SSTL15I
SSTL15II
Table 134 on page 153
for
LPDDR
12-16
2-3
9-12
Table 140,
page 160 based
186

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