Fddr Sysreg Configuration Register Summary; Fddr Sysreg Configuration Register Bit Definitions; Table 143 Fddr Sysreg; Table 144 Pll_Config_Low_1 - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
4.9.1

FDDR SYSREG Configuration Register Summary

Table 143 • FDDR SYSREG
Register Name
PLL_CONFIG_LOW_1
PLL_CONFIG_LOW_2
PLL_CONFIG_HIGH
FDDR_FACC_CLK_EN
FDDR_FACC_MUX_CONFIG
FDDR_FACC_DIVISOR_RATIO
PLL_DELAY_LINE_SEL
FDDR_SOFT_RESET
FDDR_IO_CALIB_CR
FDDR_INTERRUPT_ENABLE
F_AXI_AHB_MODE_SEL
PHY_SELF_REF_EN
FDDR_FAB_PLL_CLK_SR
FDDR_FPLL_CLK_SR
FDDR_INTERRUPT_SR
FDDR_IO_CALIB_SR
FDDR_FATC_RESET
4.9.2

FDDR SYSREG Configuration Register Bit Definitions

Table 144 • PLL_CONFIG_LOW_1
Bit
Number Name
[31:16] Reserved
Address Register
Offset Type Flash
0x500 RW P
0x504 RW P
0x508 RW P
0x50C RW P
0x510 RW P
0x514 RW P
0x518 RW P
0x51C RW P
0x520 RW P
0x524 RW P
0x528 RW P
0x52C RW P
0x530 RO –
0x534 RO –
0x53C RO –
0x544 RO –
0x548 RW P
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
Microsemi ProprietaryUG0446 User Guide Revision 7.0
Reset
Source Description
PRESETN Comes from SYSREG. Controls the
corresponding configuration input of
the FPLL.
PRESETN Comes from SYSREG. Controls the
corresponding configuration input of
the FPLL.
PRESETN Comes from SYSREG. Controls the
corresponding configuration input of
the FPLL.
PRESETN Enables the clock to the DDR memory
controller.
PRESETN Selects the standby glitch-free
multiplexers within the fabric alignment
clock controller (FACC).
PRESETN Selects the ratio between CLK_A and
CLK_DDR_FIC.
PRESETN Selects the delay values to be added to
the FPLL.
PRESETN Soft reset register for FDDR
PRESETN Configurations register for DDRIO
calibration block
PRESETN Interrupt enable register
PRESETN Selects AXI/AHB interface in the fabric.
PRESETN Automatic calibration lock is enabled.
PRESETN Indicates the lock status of the fPLL.
PRESETN Indicates the lock status of the fabric
PLL.
PRESETN Interrupt status register
PRESETN I/O calibration status register
PRESETN Reset to fabric portion of the fabric
alignment test circuit
176