Table 84 Ddrc_Lue_Syndrome_4_Sr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 84 • DDRC_LUE_SYNDROME_4_SR
Bit
Number Name
[31:16] Reserved
[15:0] DDRC_REG_ECC_SYNDROMES 0×0
Table 85 • DDRC_LUE_SYNDROME_5_SR
Bit
Number Name
[16:8] Reserved
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
72 bits are split into five registers.
[63:48] bits of DDRC_REG_ECC_SYNDROMES.
First data which has SECDED error in it. 72 bits consists of
the following:
SECDED:
[71:64] – SECDED
[63:00] – Data
In the same clock cycle, if one lane has a correctable error
and the other lane has an uncorrectable error, the syndrome
for the uncorrectable error is sent on this bus. If more than
one data lane has an error in it, the lower data lane is
selected. The priority applied when there are multiple errors
in the same cycle is as follows:
Uncorrectable error, lower lane
Uncorrectable error, upper lane
Correctable error, lower lane
Correctable error, upper lane
Only present in designs that support SECDED.
This is cleared after DDRC_ECC_INT_CLR_REG is written
over by the system.
Reset
Value
0×0
Microsemi Proprietary UG0446 User Guide Revision 7.0
Description
Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-
write operation.
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