Table 108 Ddr_Fic_Hpd_Sw_Rw_En_Cr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 107 • DDR_FIC_BUF_TIMER_CR
[31:10] Reserved
[9:0] DDR_FIC_TIMER
Table 108 • DDR_FIC_HPD_SW_RW_EN_CR
Bit
Number Name
[31:7] Reserved
6 DDR_FIC_M1_REN
5 Reserved
4 DDR_FIC_M1_WEN
3 Reserved
2 DDR_FIC_M2_REN
Reserved
1
0 DDR_FIC_M2_WEN
Table 109 • DDR_FIC_HPD_SW_RW_INVAL_CR
Bit
Number Name
[31:7] Reserved
6 DDR_FIC_flshM1
5 Reserved
4 DDR_FIC_invalid_M1
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0 10-bit timer interface used to configure timeout register. Once timer
reaches the timeout value, a flush request is generated by the flush
controller in the DDR_FIC. This port is common for all buffers.
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0 1: Enable read buffer for AHBL master1.
0: Disable read buffer for AHBL master1.
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0 1: Enable write buffer for AHBL master1.
0: Disable write buffer for AHBL master1.
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0 1: Enable read buffer for AHBL master2.
0: Disable read buffer for AHBL master2.
0×0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
0×0 1: Enable write buffer for AHBL master2.
0: Disable write buffer for AHBL master2.
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0 1: Flush read buffer for AHBL master1.
0: Default
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0 1: Invalidate write buffer for AHBL master1.
0: Default
Microsemi Proprietary UG0446 User Guide Revision 7.0 106