Microchip Technology Microsemi SmartFusion2 User Manual page 115

MDDR Subsystem
Table 104 • DDR_FIC Configuration Register Summary (continued)
Register Name
DDR_FIC_NUM_AHB_MASTERS_CR
DDR_FIC_HPB_ERR_ADDR_1_SR
DDR_FIC_HPB_ERR_ADDR_2_SR
DDR_FIC_SW_ERR_ADDR_1_SR
DDR_FIC_SW_ERR_ADDR_2_SR
DDR_FIC_HPD_SW_WRB_EMPTY_S
R
DDR_FIC_SW_HPB_LOCKOUT_SR
DDR_FIC_SW_HPD_WERR_SR
DDR_FIC_LOCK_TIMEOUTVAL_1_CR
DDR_FIC_LOCK_TIMEOUTVAL_2_CR
DDR_FIC_LOCK_TIMEOUT_EN_CR
DDR_FIC_RDWR_ERR_SR
Addres
s Offset R/W
0×41C RW
0×420 RO
0×424 RO
0×428 RO
0×42C RO
0×430 RO
0×434 RO
0×438 RO
0×440 RW
0×444 RW
0×448 RW
0×460 RO
Microsemi Proprietary UG0446 User Guide Revision 7.0
Reset
Source Description
PRESET_ Defines whether one or two AHBL 32-bit
N masters are implemented in fabric.
PRESET_ Tag of write buffer for which error response is
N received is placed in this register.
PRESET_ Tag of write buffer for which error response is
N received is placed in this register.
PRESET_ Tag of write buffer for which error response is
N received is placed in this register.
PRESET_ Tag of write buffer for which error response is
N received is placed in this register.
PRESET_ Indicates valid data in read and write buffer
N for AHBL master1 and master2.
PRESET_ Write and read buffer status register for AHBL
N master1 and master2.
PRESET_ Error response register for bufferable write
N request
PRESET_ Indicates maximum number of cycles a
N master can hold the bus for locked transfer.
PRESET_ Indicates maximum number of cycles a
N master can hold the bus for locked transfer.
PRESET_ Lock timeout feature enable register
N
PRESET_ Indicates read address of math error register.
N
104