Microchip Technology Microsemi SmartFusion2 User Manual page 168

Fabric DDR Subsystem
4.6.10.2 SECDED
To enable SECDED mode, set the REG_DDRC_MODE bits to 101 in DDRC_MODE_CR,
page 68. The PHY_DATA_SLICE_IN_USE_CR register
enable data slice 4 of the PHY.
The register value REG_DDRC_LPR_NUM_ENTRIES in the performance register,
DDRC_PERF_PARAM_1_CR
mode (without SECDED).
4.6.10.3 Read Write Latencies
The read and write latencies between DDR controller and DDR PHY can be configured. Configure the
PHY_DATA_SLICE_IN_USE_CR register for adding latencies for read and writes
4.6.10.4 Performance
The DDR controller has several performance registers which can be used to increase the speed of the
read and write transactions to DDR memory.
The DDR controller has a transaction store, shared for low and high priority transactions. The
DDRC_PERF_PARAM_1_CR register
transaction store between the low and high priority transactions. For example, if the
REG_DDRC_LPR_NUM_ENTRIES field
more time to high priority transactions. The ratio for LPR: HPR is 1:7 (as the transaction store depth is 8).
The DDRC_HPR_QUEUE_PARAM_1_CR
(Table 68, page 86), and DDRC_WR_QUEUE_PARAM_CR
configured for the minimum clock values for treating the transactions in the HPR, LPR, and WR queue as
critical and non-critical.
To force all incoming transactions to low priority, configure the DDRC_PERF_PARAM_2_CR register
(Table 71, page 87). By default it is configured to force all the incoming transactions to low priority.
4.6.10.5 Refresh Controls
The DDR controller automatically issues refresh commands to DDR memory for every tRFC (min). The
DDR controller can be programmed to issue single refreshes at a time
(REG_DDRC_REFRESH_BURST = 0) TO MINIMIZE THE WORST-CASE IMPACT OF A FORCED
REFRESH CYCLE. It can be programmed to burst the maximum number of refreshes allowed for DDR
(REFRESH_BURST = 7, for performing 8 refreshes at a time) to minimize the bandwidth lost when
refreshing the pages.
4.6.10.6 1T or 2T Timing
The DRAM can be used in 1T or 2T Timing mode by configuring the DDRC_PERF_PARAM_3_CR
register (Table 72,
controller can issue a new command on every clock cycle. In 2T timing the DDR controller will hold the
address and command bus valid for two clock cycles. This reduces the efficiency of the bus to one
command per two clocks, but it doubles the amount of setup and hold time. The data bus remains the
same for all of the variations in the address bus, Default configuration is 1T timing mode.
4.6.10.7 ODT Controls
The ODT for a specific rank of memory can be enabled or disabled by configuring the
DDRC_ODT_PARAM_1_CR
registers. These must be configured before taking the controller out of soft reset. They are applied to
every read or write issued by the controller.
4.6.10.8 Soft Resets
Set the REG_DDRC_SOFT_RSTB bit of DDRC_DYN_SOFT_RESET_CR
reset the DDR controller. To release the DDR controller from reset, set the REG_DDRC_SOFT_RSTB bit
of DDRC_DYN_SOFT_RESET_ALIAS_CR
(Table 65, page 84), must be increased by 1 to the value used in Normal
(Table 65,
(Table 65,
(Table 66,
page 88). The address bus can be clocked using 1T or 2T clocking. With 1T, the DDR
(Table 54, page 78) and DDRC_ODT_PARAM_2_CR
(Table 76,
Microsemi ProprietaryUG0446 User Guide Revision 7.0
(Table 103, page 103) must be configured to
page 84) can be configured for allocating the
page 84) is configured to 0, the controller allocates
page 86), DDRC_LPR_QUEUE_PARAM_1_CR
(Table 70, page 87) registers can be
(Table 29,
page 89) to 1.
Table 33,
(Table 103, page 103).
(Table 55, page 80)
page 67) to 0 to
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